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AC/DC 和 DC/DC 控制器 (外部 FET)

TPS53625

現行

適用於 VR12.0 微伺服器的 2 相 D-CAP+™ 降壓控制器

立即訂購
產品規格表

TPS53625

現行
產品規格表 立即訂購

產品詳細資料

Vin (min) (V) 4.5 Vin (max) (V) 24 Iout (max) (A) 60 Operating temperature range (°C) -40 to 105 Control mode D-CAP+ Topology Multiphase Rating Catalog Vout (min) (V) 0.5 Vout (max) (V) 1.52 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, SVID, Synchronous Rectification Iq (typ) (µA) 10000 Duty cycle (max) (%) 30 Number of phases 2
Vin (min) (V) 4.5 Vin (max) (V) 24 Iout (max) (A) 60 Operating temperature range (°C) -40 to 105 Control mode D-CAP+ Topology Multiphase Rating Catalog Vout (min) (V) 0.5 Vout (max) (V) 1.52 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, SVID, Synchronous Rectification Iq (typ) (µA) 10000 Duty cycle (max) (%) 30 Number of phases 2
VQFN (RSM) 32 16 mm² 4 x 4
  • VR12.0 serial VID (SVID) compliant
  • 1- or 2-phase operation
  • Supports both zero-load and non-zero-load line applications
  • 8-Bit DAC output range: 0.25 V to 1.52 V
  • Optimized efficiency at light and heavy loads
  • 8 independent levels of overshoot reduction (OSR) and undershoot reduction (USR)
  • Driverless configuration for efficient high-frequency switching
  • Supports discrete, Power Block, Power Stage or DrMOS MOSFET implementations
  • Accurate, adjustable voltage positioning
  • 300-kHz to 1-MHz frequency selections
  • Patented AutoBalance Phase Balancing
  • Selectable 8-level current limit
  • 4.5-V to 28-V conversion voltage range
  • Small, 4 mm × 4 mm, 32-Pin, VQFN PowerPAD™ integrated circuit package
  • VR12.0 serial VID (SVID) compliant
  • 1- or 2-phase operation
  • Supports both zero-load and non-zero-load line applications
  • 8-Bit DAC output range: 0.25 V to 1.52 V
  • Optimized efficiency at light and heavy loads
  • 8 independent levels of overshoot reduction (OSR) and undershoot reduction (USR)
  • Driverless configuration for efficient high-frequency switching
  • Supports discrete, Power Block, Power Stage or DrMOS MOSFET implementations
  • Accurate, adjustable voltage positioning
  • 300-kHz to 1-MHz frequency selections
  • Patented AutoBalance Phase Balancing
  • Selectable 8-level current limit
  • 4.5-V to 28-V conversion voltage range
  • Small, 4 mm × 4 mm, 32-Pin, VQFN PowerPAD™ integrated circuit package

The TPS53625 device is a driverless, fully SVID compliant, VR12.0 step-down controller. Advanced control features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance and high efficiency. The TPS53625 device also supports single-phase operation in CCM or DCM for light-load efficiency. The TPS53625 device integrates the full complement of VR12.0 I/O features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 0 to 7. Adjustable control of VOUT slew rate and voltage positioning round out the VR12.0 features. Paired with the TPS51604 FET gate driver, the solution delivers exceptionally high speed and low switching loss. The TPS53625 device works with selected TI power stage products for optimum efficiency as well as DrMOS products. The TPS53625 device operates with a default boot voltage of 1 V. Applications can override the default boot voltage by including an external resistor divider in the design.The TPS53625 device package is a space saving, thermally enhanced 32-pin VQFN package that operates from –40°C to 105°C.

The TPS53625 device is a driverless, fully SVID compliant, VR12.0 step-down controller. Advanced control features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance and high efficiency. The TPS53625 device also supports single-phase operation in CCM or DCM for light-load efficiency. The TPS53625 device integrates the full complement of VR12.0 I/O features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 0 to 7. Adjustable control of VOUT slew rate and voltage positioning round out the VR12.0 features. Paired with the TPS51604 FET gate driver, the solution delivers exceptionally high speed and low switching loss. The TPS53625 device works with selected TI power stage products for optimum efficiency as well as DrMOS products. The TPS53625 device operates with a default boot voltage of 1 V. Applications can override the default boot voltage by including an external resistor divider in the design.The TPS53625 device package is a space saving, thermally enhanced 32-pin VQFN package that operates from –40°C to 105°C.
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類型 標題 日期
* Data sheet TPS53625 Short datasheet 2022年 4月 13日

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參考設計

TIDA-00507 — 適用於微伺服器之 Intel Atom C2000 SoC VCCP 和 VNN 軌的高功率密度 9 至 15V 參考設計

The TI TPS53625 VR12 reference design (TIDA-00507), supporting Intel® Atom™ C2000, uses TI's driverless PWM architecture with TI power stages for high power density, high efficiency, and low component count while meeting Intel voltage tolerance requirements with low ripple and high (...)
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VQFN (RSM) 32 Ultra Librarian
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