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TPS536C5

現行

具適用於 AMD 平台的 SVI3 及 PMBus 的 12 相數位降壓式多相控制器

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TPS536C5

現行
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產品詳細資料

Vin (min) (V) 4.5 Vin (max) (V) 17 Iout (max) (A) 765 Operating temperature range (°C) -40 to 105 Control mode D-CAP+ Topology Multiphase Rating Catalog Vout (min) (V) 0.25 Vout (max) (V) 5.5 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Multiple Outputs, Output discharge, PMBus, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, UVLO adjustable Iq (typ) (µA) 60000 Number of phases 12
Vin (min) (V) 4.5 Vin (max) (V) 17 Iout (max) (A) 765 Operating temperature range (°C) -40 to 105 Control mode D-CAP+ Topology Multiphase Rating Catalog Vout (min) (V) 0.25 Vout (max) (V) 5.5 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Light Load Efficiency, Multiple Outputs, Output discharge, PMBus, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, UVLO adjustable Iq (typ) (µA) 60000 Number of phases 12
VQFN (RSL) 48 36 mm² 6 x 6
  • Input voltage range: 4.5 V to 17 V
  • Output voltage range: 0.25 V to 5.5 V
  • Dual output supporting N+M ≤ 12 phases, M ≤ 6 phases
  • Native trans-inductor voltage regulator (TLVR) topology support
  • AMD SVI3 compliant
  • Enhanced D-CAP+™ control to provide superior transient performance with excellent dynamic current sharing
  • Programmable loop compensations
  • Flexible phase-firing sequencing
  • Individual phase current calibrations and reports
  • Dynamic phase shedding with programmable current threshold for optimizing efficiency at light and heavy loads
  • Fast phase-adding for undershoot reduction
  • Driverless configuration for efficient high-frequency switching
  • Fully compatible with TI NexFET™ power stages for high-density solutions
  • Accurate, adjustable voltage positioning
  • Patented AutoBalance™ phase current balancing
  • Selectable per-phase current limit
  • PMBus™ system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • 6.00 × 6.00 mm, 48-pin, 0.4 mm pitch, QFN package
  • Input voltage range: 4.5 V to 17 V
  • Output voltage range: 0.25 V to 5.5 V
  • Dual output supporting N+M ≤ 12 phases, M ≤ 6 phases
  • Native trans-inductor voltage regulator (TLVR) topology support
  • AMD SVI3 compliant
  • Enhanced D-CAP+™ control to provide superior transient performance with excellent dynamic current sharing
  • Programmable loop compensations
  • Flexible phase-firing sequencing
  • Individual phase current calibrations and reports
  • Dynamic phase shedding with programmable current threshold for optimizing efficiency at light and heavy loads
  • Fast phase-adding for undershoot reduction
  • Driverless configuration for efficient high-frequency switching
  • Fully compatible with TI NexFET™ power stages for high-density solutions
  • Accurate, adjustable voltage positioning
  • Patented AutoBalance™ phase current balancing
  • Selectable per-phase current limit
  • PMBus™ system interface for telemetry of voltage, current, power, temperature, and fault conditions
  • 6.00 × 6.00 mm, 48-pin, 0.4 mm pitch, QFN package

The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCORE slew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.

The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCORE slew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.

The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.
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TPS53685 現行 具適用於 AMD 平台的 SVI3 及 PMBus 的八相數位降壓式多相控制器 TPS536C5 has higher phase count of 12 compared to TPS53685 which has 8 phases

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* Data sheet TPS536C5 Dual-Channel (N + M ≤ 12 phase) D-CAP+, Step-Down, Multiphase Controller with AMD-SVI3 and PMBus Interfaces datasheet PDF | HTML 2022年 5月 31日

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