TPS704

現行

具電源良好與獨立啟用功能的 1-A 雙通道超低壓降電壓穩壓器

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產品規格表

document-pdfAcrobat Dual-Output Low Dropout Voltage Regulators With Integrated SVS for Split Voltage datasheet (Rev. F) (英文)

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TPS7A88

現行

1-A、低雜訊、高 PSRR、雙通道可調式超低壓降電壓穩壓器 Lower noise and higher PSRR in a small 4 x 4 VQFN package

TPS704

現行

產品規格表

立即訂購

產品詳細資料

Output options

Adjustable Output, Dual output, Fixed Output

Iout (max) (A)

1

Vin (max) (V)

6

Vin (min) (V)

2.7

Vout (max) (V)

5.5

Vout (min) (V)

1.2

Fixed output options (V)

1.2, 1.5, 1.8, 2.5, 3.3

Noise (µVrms)

78

Iq (typ) (mA)

0.185

Thermal resistance θJA (°C/W)

32

Rating

Catalog

Load capacitance (min) (µF)

22

Regulated outputs (#)

2

Features

Enable, Output discharge, Power good

Accuracy (%)

2

PSRR at 100 KHz (dB)

22

Dropout voltage (Vdo) (typ) (mV)

160

Operating temperature range (°C)

-40 to 125

Output options

Adjustable Output, Dual output, Fixed Output

Iout (max) (A)

1

Vin (max) (V)

6

Vin (min) (V)

2.7

Vout (max) (V)

5.5

Vout (min) (V)

1.2

Fixed output options (V)

1.2, 1.5, 1.8, 2.5, 3.3

Noise (µVrms)

78

Iq (typ) (mA)

0.185

Thermal resistance θJA (°C/W)

32

Rating

Catalog

Load capacitance (min) (µF)

22

Regulated outputs (#)

2

Features

Enable, Output discharge, Power good

Accuracy (%)

2

PSRR at 100 KHz (dB)

22

Dropout voltage (Vdo) (typ) (mV)

160

Operating temperature range (°C)

-40 to 125

HTSSOP (PWP)

24

49.92 mm² 7.8 x 6.4

Dual Output Voltages for Split-Supply Applications
Independent Enable Functions (See Part Number TPS703xx
for Sequenced Outputs)
Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2
Fast Transient Response
Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V,
3.3-V/1.2-V, and Dual Adjustable Outputs
Open Drain Power-On Reset with 120-ms Delay
Open Drain Power Good for Regulator 1 and Regulator 2
Ultralow 185µA (typ) Quiescent Current
2µA Input Current During Standby
Low Noise: 78µV_RMS Without Bypass Capacitor
Quick Output Capacitor Discharge Feature
One Manual Reset Input
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
24-Pin PowerPAD™ TSSOP Package
Thermal Shutdown Protection

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

Dual Output Voltages for Split-Supply Applications
Independent Enable Functions (See Part Number TPS703xx
for Sequenced Outputs)
Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2
Fast Transient Response
Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V,
3.3-V/1.2-V, and Dual Adjustable Outputs
Open Drain Power-On Reset with 120-ms Delay
Open Drain Power Good for Regulator 1 and Regulator 2
Ultralow 185µA (typ) Quiescent Current
2µA Input Current During Standby
Low Noise: 78µV_RMS Without Bypass Capacitor
Quick Output Capacitor Discharge Feature
One Manual Reset Input
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
24-Pin PowerPAD™ TSSOP Package
Thermal Shutdown Protection

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

The TPS704xx family of devices consists of dual-output, low-dropout voltage regulators with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 1 A and 2 A by regulator 1 and regulator 2 respectively. Quiescent current is typically 185 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution.

The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-µF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2 µA at T_J = +25°C.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage condition at V_OUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at V_OUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.

The TPS704xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up, RESET goes into a high impedance state (that is, logic high) after a 120-ms delay when both of the following conditions are met. First, V_IN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor V_OUT1, the PG1 output pin can be connected to MR. To monitor V_OUT2, the PG2 output pin can be connected to MR. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left floating.

Internal bias voltages are powered by V_IN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.