TPS74301
- Track Pin Allows for Flexible Power-Up Sequencing
- 1% Accuracy Over Line, Load, and Temperature
- Supports Input Voltages as Low as 0.9V with External Bias Supply
- Adjustable Output (0.8V to 3.6V)
- Ultra-Low Dropout:
- 55mV at 1.5A (typ)
- Stable with any output capacitor ≥ 2.2µF (new chip)
- Stable with any or no Output Capacitor (legacy chip)
- Excellent Transient Response
- Available in 5mm × 5mm × 1mm QFN and DDPAK-7 Packages
- Open-Drain Power-Good
- Active High Enable
The TPS743 low-dropout (LDO) linear regulator provides an easy-to-use robust power management design for a wide variety of applications. The TRACK pin allows the output to track an external supply. This feature is useful in minimizing the stress on ESD structures that are present between the CORE and I/O power pins of many processors. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.
A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2µF. Each LDO is stable with low-cost ceramic output capacitors and the family is fully specified from –40°C to 125°C.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TPS74301 1.5A Ultra-LDO With Programmable Sequencing datasheet (Rev. L) | PDF | HTML | 2024年 12月 9日 |
Application note | LDO Noise Demystified (Rev. B) | PDF | HTML | 2020年 8月 18日 | |
Application note | A Topical Index of TI LDO Application Notes (Rev. F) | 2019年 6月 27日 | ||
Selection guide | Low Dropout Regulators Quick Reference Guide (Rev. P) | 2018年 3月 21日 | ||
Application note | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 2017年 8月 9日 | |
Application note | Using New Thermal Metrics | 2009年 12月 15日 | ||
Analog Design Journal | Q3 2007 Issue Analog Applications Journal | 2007年 8月 10日 | ||
Analog Design Journal | Simultaneous power-down sequencing with the TPS74x01 family of linear regulators | 2007年 8月 10日 | ||
Analog Design Journal | A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W | 2006年 10月 10日 | ||
EVM User's guide | TPS74x01EVM-118 User's Guide | 2006年 6月 20日 |
設計與開發
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TPS74301EVM-118 — TPS74301 評估模組
The TPS74301EVM-118 evaluation module (EVM) is designed to help the user easily evaluate and test the operation and functionality of the TPS74301 LDO linear regulator. The EVM uses the TPS74301, 1.5 A linear regulator with tracking and integrated power good (PG). Refer to the (...)
5V/12V Input DM6467 (x2) Power Ref Design Using a DCDC Controller & Converter
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TO-263 (KTW) | 7 | Ultra Librarian |
VQFN (RGW) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。