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線性與低壓差 (LDO) 穩壓器

TPS74901

現行

具電源良好與啟用功能的 3-A、低 VIN (0.8-V) 可調式超低壓降電壓穩壓器

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產品規格表

TPS74901

現行
產品規格表 立即訂購

產品詳細資料

Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 20 PSRR at 100 KHz (dB) 28 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 34, 36 Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 60, 120 Operating temperature range (°C) -40 to 125
Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 20 PSRR at 100 KHz (dB) 28 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 34, 36 Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 60, 120 Operating temperature range (°C) -40 to 125
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGW) 20 25 mm² 5 x 5 VSON (DRC) 10 9 mm² 3 x 3
  • VOUT range: 0.8V to 3.6V
  • Ultra-low VIN range: 0.8V to 5.5V
  • VBIAS range: 2.7V to 5.5V
  • Low dropout: 120mV (typical) at 3A
  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Accuracy over line, load, and temperature: 1% (new chip)
  • Accuracy over line, load, and temperature: 2% (legacy chip)
  • Adjustable start-up in-rush control
  • VBIAS permits low VIN operation with good transient response
  • Stable with any output capacitor ≥ 2.2µF
  • Packages:
    • Small, 3mm × 3mm × 1mm VSON
    • 5mm × 5mm × 1mm VQFN and DDPAK-7
  • Active high enable
  • VOUT range: 0.8V to 3.6V
  • Ultra-low VIN range: 0.8V to 5.5V
  • VBIAS range: 2.7V to 5.5V
  • Low dropout: 120mV (typical) at 3A
  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Accuracy over line, load, and temperature: 1% (new chip)
  • Accuracy over line, load, and temperature: 2% (legacy chip)
  • Adjustable start-up in-rush control
  • VBIAS permits low VIN operation with good transient response
  • Stable with any output capacitor ≥ 2.2µF
  • Packages:
    • Small, 3mm × 3mm × 1mm VSON
    • 5mm × 5mm × 1mm VQFN and DDPAK-7
  • Active high enable

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows a solution to be configured that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2µF, and the device is fully specified from –40°C to +125°C. The TPS74901 is offered in a small (3mm × 3mm) VSON package and a small (5mm × 5mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows a solution to be configured that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2µF, and the device is fully specified from –40°C to +125°C. The TPS74901 is offered in a small (3mm × 3mm) VSON package and a small (5mm × 5mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.
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TPS7A84 現行 具有高準確度且具有電源良好功能的 3-A、低 VIN、低雜訊、超低壓差電壓穩壓器 TPS7A84 is the next-generation version of this device with lower noise.

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類型 標題 日期
* Data sheet TPS74901 3A, Low Dropout Linear Regulator With Programmable Soft-Start datasheet (Rev. K) PDF | HTML 2024年 6月 21日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 2018年 3月 21日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
Analog Design Journal Q2 2009 Issue Analog Applications Journal 2009年 5月 1日
Analog Design Journal Taming linear-regulator inrush currents 2009年 5月 1日
EVM User's guide TPS74901EVM-210 (Rev. B) 2008年 7月 24日
EVM User's guide TPS74901EVM-210 2007年 4月 14日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TPS74901EVM-210 — 適用 3-A 低 VIN (0.8-V) 可調式超低壓降電壓穩壓器的 TPS74901 評估模組

TPS74901EVM-210 可幫助 TPS74901 低壓降線性穩壓器 IC 評估。

這些穩壓器需要低功耗偏壓 VBIAS 和電源輸入電壓 VIN。穩壓器可提供最低 0.8 V 的輸出電、輸出最高 3 A 電流，並擁有整合式監控電路及開汲極輸出，可在輸出電壓達到穩壓 (電源良好或 PG) 時進入高阻抗狀態。

使用指南: PDF
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模擬型號

TPS74901 PSpice Transient Model (Rev. B)

SLIM031B.ZIP (60 KB) - PSpice Model
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模擬型號

TPS74901 TINA-TI Transient Reference Design

SLIM257.TSC (94 KB) - TINA-TI Spice Model
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模擬型號

TPS74901 TINA-TI Transient Spice Model

SLIM256.ZIP (35 KB) - TINA-TI Spice Model
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模擬型號

TPS74901 Unencrypted PSpice Transient Model

SBVM634.ZIP (3 KB) - PSpice Model
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參考設計

TIDA-00431 — 採用 8 GHz DC 耦合差動放大器的射頻取樣 4 GSPS ADC 參考設計

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Design guide: PDF
電路圖: PDF
參考設計

TIDA-01017 — 適用於示波器、無線測試器和雷達的高速多通道 ADC 時鐘參考設計

The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01015 — 適用於數位示波器和無線測試器中的 12 位元高速 ADC 的 4 GHz 時鐘參考設計

The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00826 — 50 Ohm 2 GHz 示波器前端參考設計

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00432 — 使用適用於相位陣列雷達系統的 Xilinx 平台，將 JESD204B Giga-Sample ADC 同步化

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00359 — 適用於 GSPS ADC 的時鐘解決方案參考設計

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TO-263 (KTW) 7 Ultra Librarian
VQFN (RGW) 20 Ultra Librarian
VSON (DRC) 10 Ultra Librarian
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