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線性與低壓差 (LDO) 穩壓器

TPS754

現行

具電源良好與啟用功能的 2-A、超低壓降電壓穩壓器

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產品規格表

現在提供此產品的更新版本

open-in-new 比較替代產品
功能相同，但引腳輸出與所比較的裝置不同
TPS7A52 現行 2-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差 (LDO) 電壓穩壓器 Lower noise performance in smaller enhanced QFN package

TPS754

現行
產品規格表 立即訂購

產品詳細資料

Output options Adjustable Output, Fixed Output Iout (max) (A) 2 Vin (max) (V) 5.5 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3 Rating Catalog Noise (µVrms) 60 PSRR at 100 KHz (dB) 15 Iq (typ) (mA) 0.07 Thermal resistance θJA (°C/W) 43 Load capacitance (min) (µF) 47 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 210 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 2 Vin (max) (V) 5.5 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3 Rating Catalog Noise (µVrms) 60 PSRR at 100 KHz (dB) 15 Iq (typ) (mA) 0.07 Thermal resistance θJA (°C/W) 43 Load capacitance (min) (µF) 47 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 210 Operating temperature range (°C) -40 to 125
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4
  • 2-A Low-Dropout Voltage Regulator
  • Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
  • Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
  • Open Drain Power-Good (PG) Status Output (TPS754xxQ)
  • Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
  • Ultralow 75-µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection
  • APPLICATIONS
    • Telecom
    • Servers
    • DSP, FPGA Supplies

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
  • 2-A Low-Dropout Voltage Regulator
  • Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
  • Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
  • Open Drain Power-Good (PG) Status Output (TPS754xxQ)
  • Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
  • Ultralow 75-µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection
  • APPLICATIONS
    • Telecom
    • Servers
    • DSP, FPGA Supplies

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.

The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.

The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.

The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.

The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.

The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.
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技術文件

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類型 標題 日期
* Data sheet Fast-Transient-Response 2-A Low-Dropout Voltage Regulators datasheet (Rev. C) 2007年 10月 19日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note PowerPAD™ Thermally Enhanced Package (Rev. H) 2018年 7月 6日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日

設計與開發

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參考設計

TIDA-00207 — 符合 EN55011 規範、工業溫度、10/100Mbps 乙太網路 PHY 磚參考設計

This Ethernet PHY Brick reference design enables Texas Instruments customers to quickly design systems and release them to market, using TI industrial Ethernet PHY transceiver devices, fully compliant to EN5501 Class A EMI requirements. A 50 Pin Interface has been provided to interface with 32-Bit (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00928 — 採用光纖或雙絞線介面、符合 EMI/EMC 規範的 10/100 Mbps 乙太網路 Brick 參考設計

此乙太網路磚型參考設計提供的簡化解決方案，無需使用多個電路板以因應銅或光纖介面。其使用小尺寸、低功率的 10/100 Mbps 乙太網路收發器以縮減電路板尺寸，進而實現成本最佳化且可擴充的解決方案，並且減少在高溫工業應用中的耗電量。DP83822 提供所有必要的實體層功能，以透過兩條標準雙絞線傳輸和接收資料，或是連接至外部光纖（SC、ST 或 SFP）收發器。此設計可讓您選擇使用固定或可編程 LDO 來配置類比與 IO 電源的不同電源供應位準。磚型設計為透過內部 MAC 介接至 TM4C129X TIVA™ MCU。此設計為根據 IEC61000-4 標準等級 4 對輻射放射、ESD 和 (...)
Design guide: PDF
電路圖: PDF
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HTSSOP (PWP) 20 Ultra Librarian
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