TPS767

現行

具有啟用與延遲重設功能的 1-A、10-V、低壓差電壓穩壓器

產品詳細資料

Output options Adjustable Output, Fixed Output Iout (max) (A) 1 Vin (max) (V) 10 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5, 5.5 Rating Catalog Noise (µVrms) 55 PSRR at 100 KHz (dB) 29 Iq (typ) (mA) 0.08 Thermal resistance θJA (°C/W) 33.9, 106.9 Load capacitance (min) (µF) 10 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 230 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 1 Vin (max) (V) 10 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 2.7, 2.8, 3, 3.3, 5, 5.5 Rating Catalog Noise (µVrms) 55 PSRR at 100 KHz (dB) 29 Iq (typ) (mA) 0.08 Thermal resistance θJA (°C/W) 33.9, 106.9 Load capacitance (min) (µF) 10 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 230 Operating temperature range (°C) -40 to 125
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4 SOIC (D) 8 29.4 mm² 4.9 x 6
  • 1 A Low-Dropout Voltage Regulator
  • Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
  • Dropout Voltage Down to 230 mV at 1 A (TPS76750)
  • Ultralow 85 µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • Open Drain Power-On Reset With 200-ms Delay (See TPS768xx for PG Option)
  • 8-Pin SOIC and 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection

All trademarks are the property of their respective owners.

  • 1 A Low-Dropout Voltage Regulator
  • Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
  • Dropout Voltage Down to 230 mV at 1 A (TPS76750)
  • Ultralow 85 µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • Open Drain Power-On Reset With 200-ms Delay (See TPS768xx for PG Option)
  • 8-Pin SOIC and 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection

All trademarks are the property of their respective owners.

This device is designed to have a fast transient response and be stable with 10 µF low ESR capacitors. This combination provides high performance at a reasonable cost.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
230 mV at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically
85 µA over the full range of output current, 0 mA to
1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.

The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages.

This device is designed to have a fast transient response and be stable with 10 µF low ESR capacitors. This combination provides high performance at a reasonable cost.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
230 mV at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically
85 µA over the full range of output current, 0 mA to
1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.

The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 20-pin PWP packages.

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技術文件

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檢視所有 6
類型 標題 日期
* Data sheet TPS767xxQ Fast-Transient-Response 1-A Low-Dropout Linear Regulators datasheet (Rev. J) PDF | HTML 2015年 8月 6日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note PowerPAD™ Thermally Enhanced Package (Rev. H) 2018年 7月 6日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
User guide Voltage-Controlled Amplifier Evaluation Kit 2008年 8月 25日
Application note Power Supply Sequencing Solutions for Dual Supply Voltage DSPs (Rev. A) 2000年 7月 5日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

TPS76701Q PSpice Transient Model

SLVMB35.ZIP (89 KB) - PSpice Model
模擬型號

TPS76701Q Unencrypted PSpice Transient Model

SLVMB34.ZIP (3 KB) - PSpice Model
模擬型號

TPS76715Q PSpice Transient Model

SLVMB13.ZIP (83 KB) - PSpice Model
模擬型號

TPS76715Q Unencrypted PSpice Transient Model

SLVMB12.ZIP (2 KB) - PSpice Model
模擬型號

TPS76718Q PSpice Transient Model

SLVMB24.ZIP (80 KB) - PSpice Model
模擬型號

TPS76718Q Unencrypted PSpice Transient Model

SLVMB25.ZIP (2 KB) - PSpice Model
模擬型號

TPS76725Q PSpice Transient Model

SLVMB20.ZIP (80 KB) - PSpice Model
模擬型號

TPS76725Q Unencrypted PSpice Transient Model

SLVMB21.ZIP (2 KB) - PSpice Model
模擬型號

TPS76727Q PSpice Transient Model

SLVMB16.ZIP (80 KB) - PSpice Model
模擬型號

TPS76727Q Unencrypted PSpice Transient Model

SLVMB17.ZIP (2 KB) - PSpice Model
模擬型號

TPS76728Q PSpice Transient Model

SLVMB18.ZIP (83 KB) - PSpice Model
模擬型號

TPS76728Q Unencrypted PSpice Transient Model

SLVMB19.ZIP (2 KB) - PSpice Model
模擬型號

TPS76730Q PSpice Transient Model

SLVMB27.ZIP (83 KB) - PSpice Model
模擬型號

TPS76730Q Unencrypted PSpice Transient Model

SLVMB26.ZIP (2 KB) - PSpice Model
模擬型號

TPS76733Q PSpice Transient Model

SLVMB15.ZIP (78 KB) - PSpice Model
模擬型號

TPS76733Q Unencrypted PSpice Transient Model

SLVMB14.ZIP (2 KB) - PSpice Model
模擬型號

TPS76750Q PSpice Transient Model

SLVMB23.ZIP (81 KB) - PSpice Model
模擬型號

TPS76750Q Unencrypted PSpice Transient Model

SLVMB22.ZIP (2 KB) - PSpice Model
參考設計

TIDA-00078 — 具有 I/Q 校正的直接降壓轉換系統

The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00075 — 高頻寬和高電壓任意波形產生器前端

此設計展示如何使用 DAC5682Z 電流汲極輸出的主動介面,其中的典型應用包括任意波形產生器的前端。EVM 包括用於數位轉類比轉換的 DAC5682Z、用於示範使用超寬頻運算放大器的主動介面實作的 OPA695,以及展示具有大電壓擺幅的運算放大器的 THS3091 和 THS3095。電路板上也包括用於產生時脈的 CDCM7005、VCXO 和參考,以及用於電壓調節的線性穩壓器。與 EVM 的通訊可透過 USB 介面和 GUI 軟體完成。
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00074 — 寬頻射頻轉數位複雜接收器 - 回饋訊號鏈

This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00073 — 雙寬頻射頻轉數位接收器設計

The TSW1265EVM is an example design of a wideband RF to digital dual receiver solution capable of digitizing up to 125MHz of spectrum. The system provides a reference on how to use the ADS4249, LMH6521, LMK0480x, and a dual mixer to achieve this.  This reference EVEM coupled with a capture (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00068 — 具有 DPD 回饋路徑的基地台收發器

The design is for a small cell base station development platform.  It provides two real receive paths, two complex transmit paths, and a shared real feedback path.  This design has macro basestation performance, but with small cell base station footprint.  The current design handles (...)
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HTSSOP (PWP) 20 Ultra Librarian
SOIC (D) 8 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

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