TPS7A37
- Stable with 1-µF or Larger Ceramic Output
Capacitor - Input Voltage Range: 2.2 V to 5.5 V
- Ultralow Dropout Voltage:
- 200-mV Maximum at 1 A
- Excellent Load Transient Response–Even With
Only 1-µF Output Capacitor - NMOS Topology Delivers Low Reverse Leakage
Current - Excellent Accuracy:
- 0.23% Nominal Accuracy
- 1% Overall Accuracy Over Line, Over Load,
and Over Temperature
- Less Than 20-nA typical IQ in Shutdown Mode
- Thermal Shutdown and Current Limit for Fault
Protection
The TPS7A37 family of linear low-dropout (LDO) voltage regulators uses an NMOS pass element in a voltage-follower configuration. This topology is relatively insensitive to output capacitor value and ESR, allowing a wide variety of load configurations. Load transient response is excellent, even with a small 1-µF ceramic output capacitor. The NMOS topology also allows very low dropout.
The TPS7A37 family uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is under 20 nA and ideal for portable applications. These devices are protected by thermal shutdown and foldback current limit.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 1% High-Accuracy, 1-A, Low-Dropout Regulator with Reverse Current Protection datasheet (Rev. B) | 2013年 10月 23日 | |
| Application note | A Topical Index of TI LDO Application Notes (Rev. F) | 2019年 6月 27日 | ||
| Technical article | LDO Basics: Preventing reverse current | PDF | HTML | 2018年 7月 25日 | |
| Selection guide | Low Dropout Regulators Quick Reference Guide (Rev. P) | 2018年 3月 21日 | ||
| User guide | TPS7A37XXDRV-529 Evaluation Module | 2013年 1月 22日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WSON (DRV) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。