封裝資訊
| 封裝 | 針腳 DSBGA (YCG) | 25 |
| 操作溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送業者 2,500 | LARGE T&R |
TUSB2E221 的特色
- Compliance to USB 2.0 and eUSB2 (rev 1.2)
- Support for low-speed (LS), full-speed (FS), high-speed (HS)
- Best-in-class high-speed total jitter of 20ps
- Register access protocol receptor capable
- Dual independent repeater
- 2:2 crossbar mux (DSBGA package only)
- Host and device mode (DRD) support
- Selection between 1.2V and 1.8V control or I2C levels using VIOSEL pin
- Auto detection for I2C or strap-pin options
- Three strap-pins for USB 2.0 high-speed channel compensation settings
- I2C device interface for more configurations
- Device variants
- eUSB2 1.0V or 1.2V signaling interface
- Four eUSB2 trace loss compensation levels for different product form-factors: 2.5, 5, 7.5, and 10 inches
- Supports auto-resume ECR as well as L2 interrupt resume mode
- CTA-936 USB Carkit UART support
- Optional BC1.2 CDP battery charging and detection support
- Optional GPIO modes for EQ pins for debug and I2C ↔ GPIOs through EQ0/1
- I2C accessible debug capabilities for manufacturing tests
TUSB2E221 的說明
The TUSB2E221 enables implementation of USB 2.0 compliant port on newer processors using lower voltage processes.
The TUSB2E221 is a USB eUSB2-USB 2.0 repeater supporting both device and host modes. The TUSB2E221 supports USB low-speed (LS) and full-speed (FS) signals and high-speed (HS) signals.
The TUSB2E221 is designed to interface with eUSB2 eDSPr or eUSPr operating at 1.2V single-ended signaling.
The TUSB2E221 has multiple patented designs to provide robust interoperability, optimum performance, and power.
For systems without an I2C interface, the device offers eight individual settings with three strap-pins for USB 2.0 channel Equivalent Series Resistance (ESR) up to 17.5Ω. Device variants are available for different levels of eUSB2 trace length compensation up to 10 inches.
The I2C interface permits additional flexibility for fine tuning of the device’s RX and TX settings. The available settings are RX equalization, RX squelch threshold, RX disconnect thresholds, TX amplitude, TX slew rate and TX pre-emphasis.
Various debug options are available through the three EQ pins that can be configured to monitor various USB bus states or interrupt as well as CTA-936 UART mode control that can provide SoC debug capabilities. EQ0 and EQ1 can be used as general purpose I2C to GPIOs bridge.