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Fixed data center switch

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Block diagram

Fixed data center switch

Block diagram

Overview

Our integrated circuits and reference designs help you create data center switches with ultra-high bandwidth and low-power consumption. Use the interactive reference diagram below to design a high-speed Ethernet switch with the right interface, physical interface device (PHY) and power management products to support the connectivity needs of modern Ethernet switch fabrics.

Design requirements

Modern data center switch designs require:

  • Highly-efficient power solutions for the latest-generation FPGAs, ASICs and CPUs.
  • Best-in-class signal integrity for ever increasing data rates.
  • Reduced system downtime through detection and prevention of damaging conditions.
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Block diagram

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Fixed data center switch

JTAG JTAG AC AC -48V -48V HV DC Bus HV DC Bus N+1 PSU N+1 PSU DC/DC DC/DC IBV1 IBV1 Hot swap controller Hot swap controller AC/DC AC/DC IBV1 IBV1 FET FET Bus converter (optional) Bus converter (optional) eFuse eFuse DC/DC DC/DC IBV2 IBV2 POL power (FPGA, ASIC, merchant Si, clocks, etc.) POL power (FPGA, ASIC, merchant Si, clocks, etc.) Converter Converter LDO LDO Multiphase controller Multiphase controller Power stage Power stage CPU & memory power CPU & memory power Multiphase controller Multiphase controller Power stage Power stage Converter Converter DDR termination DDR termination Sequencing & monitoring Sequencing & monitoring Logic Logic Power on reset Power on reset Sequencer Sequencer Clocking Clocking Clock generator Clock generator Clock buffer Clock buffer Fan control Fan control Hot swap controller Hot swap controller Fan controller Fan controller Temp sense Temp sense eFuse eFuse CPU CPU CPU CPU I2C expander I2C expander I2C lvel translator I2C lvel translator Voltage translator Voltage translator Buffer Buffer Retimer/redriver Retimer/redriver DDR DDR Switch fabric Switch fabric I2C vel translator I2C vel translator I2C expander I2C expander Voltage translator Voltage translator Latch Latch CPLD CPLD BMC BMC Power on reset Power on reset Logic Logic REF REF FPGA FPGA Temp sense Temp sense VMon VMon I2C mux I2C mux Switch ASIC / merchant silicon Switch ASIC / merchant silicon Retimer/redriver Retimer/redriver Memory Memory DDR DDR Flash Flash IO (JTAG, RS232, RS485) IO (JTAG, RS232, RS485) Buffer Buffer JTAG MUX JTAG MUX RS-232 RS-232 RS-485 RS-485 ESD ESD PHY PHY LDO LDO USB USB USB load switch USB load switch ESD ESD USB mux USB mux Buck + LS Buck + LS LED driver LED driver LED driver LED driver Shift register Shift register Logic Logic Downlink (optical interface) Downlink (optical interface) Optical module Optical module Optical module Optical module Optical module Optical module PHY PHY PHY PHY PHY PHY Retimer/redriver Retimer/redriver Retimer/redriver Retimer/redriver Retimer/redriver Retimer/redriver Front port controller Front port controller eFuse eFuse Uplink (optical interface) Uplink (optical interface) Optical module Optical module Retimer Retimer eFuse eFuse Switch Switch SPI MUX SPI MUX I2C mux I2C mux

Sequencing & monitoring

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Controls power sequencing for the entire system. This can either be implemented with the help of discrete logic gates or by using more integrated sequencer devices. TI's advanced sequencer devices allows for precise startup functionality and ensures proper startup of the other board subsystems.

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Power management (18)
Supervisor & reset ICs
  • TPS3897—Single-channel, ultra-small, adjustable supervisor with active-high, open-drain output
    Data sheet: PDF | HTML
  • TLV803E—Low-power voltage supervisor (reset IC) with active-low open-drain output
    Data sheet: PDF | HTML
  • TLV809—3-pin voltage supervisor (reset IC) with active-low, push-pull reset
    Data sheet: PDF | HTML
  • TPS3700—High-voltage (18-V) window voltage detector for overvoltage and undervoltage monitoring
    Data sheet: PDF | HTML
  • TPS3899—Nanopower supervisor with programmable sense and reset delay
    Data sheet: PDF | HTML
  • TLC77—Voltage supervisor with programmable delay time
    Data sheet: PDF | HTML
Sequencers
  • UCD90320—32-Rail PMBus Power Sequencer and System Manager
    Data sheet: PDF | HTML
  • UCD9090A—10-Rail Power Supply Sequencer and Monitor With ACPI Support
    Data sheet: PDF | HTML
  • UCD90160A—16-Rail PMBus Power Supply Sequencer and System Manager with ACPI Support
    Data sheet: PDF | HTML
  • UCD90120A—12-Rail Power Supply Sequencer and Monitor with ACPI Support
    Data sheet: PDF | HTML
  • UCD9081—Power Supply Sequencer and Monitor with Non-Volatile Error Logging
    Data sheet: PDF | HTML
  • UCD90160—16-Rail Power Supply Sequencer with ACPI Support
    Data sheet: PDF | HTML
eFuses & hot swap controllers
  • TPS1685—9V to 80V, 3.5mΩ, 20A stackable integrated hot swap (eFuse) with accurate and fast current monitor
    Data sheet: PDF | HTML
  • TPS1689—9V to 80V, 3.65mΩ, 20A stackable integrated hot swap (eFuse) with PMBus digital telemetry
    Data sheet: PDF | HTML
  • TPS25947—2.7-V to 23-V, 28-mΩ, 5.5-A eFuse with integrated reverse polarity protection
    Data sheet: PDF | HTML
  • TPS25981—2.7-V to 16-V, 10-A, 6-mΩ eFuse with transient overcurrent blanking timer
    Data sheet: PDF | HTML
  • TPS25985—4.5-V to 16-V, 0.59-mΩ, 80-A stackable compact eFuse with accurate and fast current monitor
    Data sheet: PDF | HTML
  • TPS25983—2.7V to 26V, 2.7mΩ 20A integrated hot-swap eFuse with current monitor and blocking FET drive
    Data sheet: PDF | HTML
Logic & voltage translation (27)
Voltage translators
AND gates
  • SN74LVC1G08—1-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate
    Data sheet: PDF | HTML
  • SN74LVC1G11—1-ch, 3-input 1.65-V to 5.5-V 32 mA drive strength AND gate
    Data sheet: PDF | HTML
  • SN74AHC1G09—1-ch, 2-input 2-V to 5.5-V high-speed (9 ns) AND gate with open-drain outputs
    Data sheet: PDF | HTML
  • SN74AUP1G08—1-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate
    Data sheet: PDF | HTML
  • SN74LVC2G08—2-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate
    Data sheet: PDF | HTML
  • SN74AHC1G08—1-ch, 2-input 2-V to 5.5-V high-speed (9 ns) AND gate
    Data sheet: PDF | HTML
D-type flip-flops
  • SN74LVC1G74—Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset
    Data sheet: PDF | HTML
  • SN74LVC2G74—Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset
    Data sheet: PDF | HTML
  • SN74AUP1G74—Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
    Data sheet: PDF | HTML
  • SN74LVC74A—Dual positive-edge-triggered D-type flip-flops with clear and preset
    Data sheet: PDF | HTML
OR gates
NAND gates
D-type latches
NOR gates
  • PMP21887—High-current 360-A static / 600-A peak core PMBus voltage 12-phase reference design for ASICs
    Test report: PDF Schematic: PDF

Technical documentation

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Type Title Date
Technical article Are you ready for BAW? PDF | HTML 29 Jun 2023
Application note How to use the LMK05318 as a jitter cleaner 27 Feb 2019
Application note Glitch free power sequencing with AXC level translators (Rev. A) 20 Sep 2018
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 19 Sep 2018
Application note Optimizing Layout of the TPS54824 HotRod™ Package for Thermal Performance 16 Nov 2018
Application note Interfacing Between LVPECL, VML, CML and LVDS Levels 16 Dec 2002
Application note Supported synchronization modes for TI network synchronizers (Rev. A) 11 May 2022
Application note DC/DC Point-of-load Power Solutions for Wired Networking Switch Systems 11 May 2022
Application note Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) 11 May 2022
Application note Optimizing Network Switch Designs with Common Logic Use Cases (Rev. A) PDF | HTML 10 May 2022
Analog Design Journal Understanding thermal-resistance specification of DC/DC convert. w/ MOSFETs 08 Jan 2018
White paper Internally compensated advanced current mode (ACM) (Rev. A) 07 Dec 2018
Analog Design Journal Comparing internally-compensated advanced current mode (ACM) w/ D-CAP3™ control (Rev. A) 06 Nov 2018

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