The equations describing V_E can be simplified in most cases for real world LDO's based on what nodes are accessible to the designer. We will identify these error terms in modern data sheets and later discuss their impact on current sharing in parallel LDO's.

In the simplest design scenario, the LDO contains all of the Figure 2-1(a) elements inside the integrated circuit (with either Figure 2-1(b) or Figure 2-1(c) generating the voltage reference) and the only terminals accessible to the designer are V_IN, V_OUT and return (or ground). The data sheet will provide an output accuracy specification which can be used as V_E for the parallel converter.

In the most complex design scenario, the LDO is designed from discrete components. Here, the V_OS and I_BIAS terms must be known and will be located in the discrete op-amp’s data sheet. Most designs will be somewhere in between these extreme cases, thus guidance for most designs can be generalized based on which node the designer has access to – the V_REF pin and / or the V_FB pin.