인터페이스 고속 시리얼라이저/디시리얼라이저 FPD-Link 시리얼라이저/디시리얼라이저

DS90C383B

활성

+3.3V 프로그래머블 LVDS 트랜스미터 24비트 평면 패널 디스플레이(FPD) 링크 - 65MHz

제품 상세 정보

Function Serializer Color depth (bpp) 24 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) Rating Catalog Operating temperature range (°C) -10 to 70
Function Serializer Color depth (bpp) 24 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spread
  • "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high
  • 18 to 68 MHz shift clock support
  • Best-in-Class Setup and Hold Times on TxINPUTs
  • Tx power consumption < 130 mW (typ) at 65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-down mode < 60μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow bus reduces cable size and cost
  • Up to 1.8 Gbps throughput
  • Up to 227 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compatible with TIA/EIA-644 LVDS standard
  • Low profile 56-lead TSSOP package
  • Improved replacement for:
    • SN75LVDS83, DS90C383A

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

  • No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or -5% down spread
  • "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high
  • 18 to 68 MHz shift clock support
  • Best-in-Class Setup and Hold Times on TxINPUTs
  • Tx power consumption < 130 mW (typ) at 65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-down mode < 60μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow bus reduces cable size and cost
  • Up to 1.8 Gbps throughput
  • Up to 227 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compatible with TIA/EIA-644 LVDS standard
  • Low profile 56-lead TSSOP package
  • Improved replacement for:
    • SN75LVDS83, DS90C383A

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

The DS90C383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90C383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
8개 모두 보기
유형 직함 날짜
* Data sheet DS90C383B 3.3V Prog LVDS Trans 24-Bit FPD Link-65 MHz datasheet (Rev. G) 2013/04/17
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018/11/09
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 2018/06/29
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 2017/08/08
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 2016/01/13
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 2004/05/15
Application note AN-1056 STN Application Using FPD-Link 2004/05/14
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 2004/05/14

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
레퍼런스 디자인

TIDA-01051 — 자동 테스트 장비에 대한 FPGA 활용률 및 데이터 처리량 최적화 레퍼런스 디자인

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such (...)
Design guide: PDF
회로도: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (DGG) 56 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상