DS90CF386
- 20-MHz to 85-MHz Shift Clock Support
- Rx Power Consumption <142 mW (Typical) at
85-MHz Grayscale - Rx Power-Down Mode <1.44 mW (Maximum)
- ESD Rating >7 kV (HBM), >700 V (EIAJ)
- Supports VGA, SVGA, XGA, and Single Pixel
SXGA - PLL Requires No External Components
- Compatible With TIA/EIA-644 LVDS Standard
- Low Profile 56-Pin or 48-Pin TSSOP Package
- DS90CF386 Also Available in a 64-Pin, 0.8-mm,
Fine Pitch Ball Grid Array (NFBGA) Package
The DS90CF386 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CF366 receiver that converts three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the falling edge. A rising edge or falling edge strobe transmitter will interoperate with a falling edge strobe receiver without any translation logic.
The receiver LVDS clock operates at rates from 20 MHz to 85 MHz. The device phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 85 MHz, each LVDS input line is running at a bit rate of 595 Mbps, resulting in a maximum throughput of 2.38 Gbps for the DS90CF386 and 1.785 Gbps for the DS90CF366.
The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high-speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages. The DS90CF386 is also offered in a 64-pin, 0.8-mm, fine pitch ball grid array (NFBGA) package which provides a 44% reduction in PCB footprint compared to the 56-pin TSSOP package.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS90CF3x6 3.3-V LVDS Receiver 24-Bit Or 18-Bit Flat Panel Display (FPD) Link, 85 MHz datasheet (Rev. J) | PDF | HTML | 2016/05/31 |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/09 | ||
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018/06/29 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017/08/08 | ||
| User guide | FLINK3V8BT-85 Evaluation Kit (Rev. A) | 2016/08/24 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | 2016/01/13 | ||
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004/05/15 | ||
| Application note | AN-1056 STN Application Using FPD-Link | 2004/05/14 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004/05/14 |
설계 및 개발
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FLINK3V8BT-85 — 시리얼라이저 및 디시리얼라이저 LVDS 장치의 FPD-Link 제품군용 평가 키트
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| NFBGA (NZC) | 64 | Ultra Librarian |
| TSSOP (DGG) | 56 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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