DS90UR124
- Supports displays with 18-bit color depth
- 5MHz to 43MHz Pixel clock
- Automotive-grade product AEC-Q100 grade 2 qualified
- 24:1 Interface compression
- Embedded clock with DC balancing supports AC-coupled data transmission
- Capable to drive up to 10 meters shielded twisted-pair cable
- No reference clock required (deserializer)
- Meets ISO 10605 ESD – greater than 8kV HBM ESD structure
- Hot plug support
- EMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs
- @Speed BIST (Built-In Self-Test) to validate LVDS transmission path
- Individual power-down controls for both transmitter and receiver
- Power supply range 3.3V ±10%
- 48-pin TQFP package for transmitter and 64-pin TQFP package for receiver
- Temperature range: –40°C to 105°C
- Backward-compatible mode with DS90C241/DS90C124
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS90URxxx-Q1 5MHz to 43MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset datasheet (Rev. P) | PDF | HTML | 2024/08/29 |
| Application note | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013/04/29 | ||
| Application note | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013/04/29 | ||
| Application note | AN-1807 FPD-Link II Display SerDes Overview (Rev. B) | 2013/04/26 | ||
| Application note | AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B) | 2013/04/26 | ||
| Application note | Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) | 2013/04/26 | ||
| User guide | High Efficiency Portable Media Player (PMP) Dock Station User Guide | 2012/01/27 | ||
| User guide | DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide | 2012/01/26 | ||
| User guide | FPD to SERDES (UR) Translator Chip DS99R421 Evaluation Kit User's Guide | 2012/01/26 |
설계 및 개발
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SERDESUR-43USB — DS90UR241 DS90UR124 시리얼라이저 및 디시리얼라이저 칩셋용 평가 키트
The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.
The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TQFP (PAG) | 64 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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