AES, Byte addressable, Configurable logic block, EVITA-Full HSM, FPU64, HRPWM, Hardware encryption (AES/DES/SHA/MD5), Lockstep, Safety and security unit, TMU, Watchdog timer

UART

6

CAN (#)

6 (CAN-FD)

Sigma-delta filter

16

PWM (Ch)

36

TI functional safety category

Functional Safety-Compliant

Number of ADC channels

44, 54, 80

SPI

5

QEP

6

USB

0

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Communication interface

CAN FD, FSI, I2C, LIN, PMBUS, SENT, SPI, UART, USB

CPU

3x C29 (Lockstep Capable)

Frequency (MHz)

200

Flash memory (kByte)

4864

RAM (kByte)

452

ADC resolution (bps)

12, 16

Total processing (MIPS)

1200

Features

AES, Byte addressable, Configurable logic block, EVITA-Full HSM, FPU64, HRPWM, Hardware encryption (AES/DES/SHA/MD5), Lockstep, Safety and security unit, TMU, Watchdog timer

UART

6

CAN (#)

6 (CAN-FD)

Sigma-delta filter

16

PWM (Ch)

36

TI functional safety category

Functional Safety-Compliant

Number of ADC channels

44, 54, 80

SPI

5

QEP

6

USB

0

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Communication interface

CAN FD, FSI, I2C, LIN, PMBUS, SENT, SPI, UART, USB

NFBGA (ZEX)

256

169 mm² 13 x 13

Real-time Processing

Three C29x 64-bit CPUs (CPU1, CPU2, CPU3) running at 200MHz
- 2x signal chain performance versus C28x with improved pipeline
- Split lock and lockstep operating modes
C29x CPU architecture
- Byte addressability
- High-performance real-time control with low latency
- High-performance DSP and general-purpose processing capabilities
- VLIW CPU executes 1 to 8 instructions in parallel
- Fully protected pipeline
- 8/16/32/64-bit single-cycle memory operations, up to two 64-bit memory reads and one 64-bit memory write in a single-cycle
- IEEE 32-bit and 64-bit floating operations
- 32-bit and 64-bit trigonometric operations
- HW interrupt prioritization and nesting
- 11-cycle real-time interrupt response
- Atomic operations with memory protection
- Multi safe island code execution managed in hardware

Memory

4MB of CPU-mappable flash (ECC-protected) capable of supporting Firmware Over the Air (FOTA) with A/B swap and LFU
256KB of Data-only Flash (ECC-protected)
452KB of RAM (ECC-protected)
Dedicated 512KB Flash and 36KB RAM memories for HSM (ECC-protected)
Built in ECC logic for system-wide safety

Safety Peripherals

CPU1 and CPU2 splitlock and lockstep support
Logic Power-On Self-Test (LPOST)
Memory Power-On Self-Test (MPOST)
Error and Signaling Module (ESM)
Dual-clock Comparator (DCC)
Waveform Analyzer and Diagnostics (WADI)
Context-sensitive Memory and Peripheral Protection with SSU
Safety Interconnect (SIC)
Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 and IEC 61508; system design will be available upon production release
- Systematic capability up to ASIL D and SIL 3 targeted
- Hardware capability up to ASIL D and SIL 3 targeted
Safety-related certification
- ISO 26262 certification up to ASIL D and IEC 61508 SIL 3 by TÜV SÜD planned

Security

Hardware Security Module (HSM)
- Independently running Arm Cortex-M4 based security controller subsystem at 100MHz
- 512KB of flash (ECC-protected)
- 36KB of RAM (ECC-protected)
- Secure key storage
- Secure BOOT
- Secure Debug
- Dedicated 8-channel Real-Time Direct Memory Access (RTDMA) controller
- EVITA-full support
- FOTA with A/B swap
- Hardware cryptographic accelerators
  - Asymmetric cryptography - RSA, ECC, SM2
  - Symmetric cryptography - AES, SM4
  - Hash operations - SHA2, HMAC, SM3
  - True Random Number Generator
Safety and Security Unit (SSU)
- Advanced Real-Time Safety and Security
  - 64 Memory Access Protection Ranges per CPU
  - Up to 15 user LINKs and 7 stack pointers per CPU for hardware code isolation
  - Power-on Self-test (POST) capability
  - FOTA and LFU support with rollback control

Analog Subsystem

Five Analog-to-Digital Converters (ADCs)
- Two 16-bit ADCs, 1.19MSPS each
- Three 12-bit ADCs, 3.92MSPS each
- Up to 80 single-ended or 16 differential inputs
- 40 redundant input channels for flexibility
- Separate sample-and-hold (S/H) on each ADC for simultaneous sampling
- Hardware post-processing of conversions
- Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
- Programmable delay from SOC trigger to start of conversion
- Automatic comparison of conversion results for functional safety applications
12 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
- Connection options for internal temperature sensor and ADC reference
Two 12-bit buffered DAC outputs

Control Peripherals

36 Pulse Width Modulator (PWM) channels, all with high-resolution capability (HRPWM)
- Minimum Dead-Band Logic (MINDB)
- Illegal Combo Logic (ICL) for standard and high resolution
- Diode Emulation (DE) support
- Multilevel shadowing on XCMP
Six Enhanced Capture (eCAP) modules
- High-resolution Capture (HRCAP) available on two of the six eCAP modules
- Two new monitor units for edge, pulse width and period that can be coupled with ePWM strobes and trip events
- Increased 256 multiplexed capture inputs
- New ADC SOC generation capability
Six Enhanced Quadrature Encoder Pulse (eQEP) modules
16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
Embedded Pattern Generator (EPG)
Configurable Logic Block (CLB)
- Six tiles
- Augments existing peripheral capability
- Supports position manager solutions

Communications Peripherals

EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
Fast Serial Interface (FSI) with four transmitters and four receivers
Five high-speed (up to 50MHz) SPI ports (pin-bootable)
Six High-Speed Universal Asynchronous Receiver/Transmitters (UARTs) (pin-bootable)
Two I2C interfaces (pin-bootable)
Two Local Interconnect Network (LIN) (supports SCI)
Power-Management Bus (PMBus) interface (supports I2C)
Six Single Edge Nibble Transmission interface (SENT)
Six Controller Area Networks with Flexible Data Rate (CAN FD/MCAN) (pin-bootable)

Systems Peripherals

External Memory Interface (EMIF) with ASRAM and SDRAM support
Two 10-channel Real-Time Direct Memory Access (RTDMA) controllers with MPU
Up to 190 usable signal pins
- 136 General-Purpose Input/Output (GPIO) pins
- 80 analog pins (26 AGPIOs included in GPIOs)
Peripheral Interrupt Priority and Expansion (PIPE)
Low-power mode (LPM) support
Embedded Real-time Analysis and Diagnostic (ERAD)

Clock and System Control

On-chip crystal oscillator
Windowed watchdog timer module
Missing clock detection circuitry
1.2V core, 3.3V I/O design
- Internal VREG for 1.2V generation
- Brownout reset (BOR) circuit

Package Options:

Lead-free, green packaging
256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEX suffix], 13mm x 13mm/0.8mm pitch
176-pin Thermally Enhanced Thin Quad Flatpack (HTQFP) [PTS suffix], 22mm x 22mm/0.4mm pitch
144-pin HTQFP [RFS suffix],18mm x 18mm/0.4mm pitch
100-pin HTQFP [PZS suffix],14mm x 14mm/0.4mm pitch

Temperature

Ambient (TA): –40°C to 125°C

Real-time Processing

Three C29x 64-bit CPUs (CPU1, CPU2, CPU3) running at 200MHz
- 2x signal chain performance versus C28x with improved pipeline
- Split lock and lockstep operating modes
C29x CPU architecture
- Byte addressability
- High-performance real-time control with low latency
- High-performance DSP and general-purpose processing capabilities
- VLIW CPU executes 1 to 8 instructions in parallel
- Fully protected pipeline
- 8/16/32/64-bit single-cycle memory operations, up to two 64-bit memory reads and one 64-bit memory write in a single-cycle
- IEEE 32-bit and 64-bit floating operations
- 32-bit and 64-bit trigonometric operations
- HW interrupt prioritization and nesting
- 11-cycle real-time interrupt response
- Atomic operations with memory protection
- Multi safe island code execution managed in hardware

Memory

4MB of CPU-mappable flash (ECC-protected) capable of supporting Firmware Over the Air (FOTA) with A/B swap and LFU
256KB of Data-only Flash (ECC-protected)
452KB of RAM (ECC-protected)
Dedicated 512KB Flash and 36KB RAM memories for HSM (ECC-protected)
Built in ECC logic for system-wide safety

Safety Peripherals

CPU1 and CPU2 splitlock and lockstep support
Logic Power-On Self-Test (LPOST)
Memory Power-On Self-Test (MPOST)
Error and Signaling Module (ESM)
Dual-clock Comparator (DCC)
Waveform Analyzer and Diagnostics (WADI)
Context-sensitive Memory and Peripheral Protection with SSU
Safety Interconnect (SIC)
Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 and IEC 61508; system design will be available upon production release
- Systematic capability up to ASIL D and SIL 3 targeted
- Hardware capability up to ASIL D and SIL 3 targeted
Safety-related certification
- ISO 26262 certification up to ASIL D and IEC 61508 SIL 3 by TÜV SÜD planned

Security

Hardware Security Module (HSM)
- Independently running Arm Cortex-M4 based security controller subsystem at 100MHz
- 512KB of flash (ECC-protected)
- 36KB of RAM (ECC-protected)
- Secure key storage
- Secure BOOT
- Secure Debug
- Dedicated 8-channel Real-Time Direct Memory Access (RTDMA) controller
- EVITA-full support
- FOTA with A/B swap
- Hardware cryptographic accelerators
  - Asymmetric cryptography - RSA, ECC, SM2
  - Symmetric cryptography - AES, SM4
  - Hash operations - SHA2, HMAC, SM3
  - True Random Number Generator
Safety and Security Unit (SSU)
- Advanced Real-Time Safety and Security
  - 64 Memory Access Protection Ranges per CPU
  - Up to 15 user LINKs and 7 stack pointers per CPU for hardware code isolation
  - Power-on Self-test (POST) capability
  - FOTA and LFU support with rollback control

Analog Subsystem

Five Analog-to-Digital Converters (ADCs)
- Two 16-bit ADCs, 1.19MSPS each
- Three 12-bit ADCs, 3.92MSPS each
- Up to 80 single-ended or 16 differential inputs
- 40 redundant input channels for flexibility
- Separate sample-and-hold (S/H) on each ADC for simultaneous sampling
- Hardware post-processing of conversions
- Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
- Programmable delay from SOC trigger to start of conversion
- Automatic comparison of conversion results for functional safety applications
12 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
- Connection options for internal temperature sensor and ADC reference
Two 12-bit buffered DAC outputs

Control Peripherals

36 Pulse Width Modulator (PWM) channels, all with high-resolution capability (HRPWM)
- Minimum Dead-Band Logic (MINDB)
- Illegal Combo Logic (ICL) for standard and high resolution
- Diode Emulation (DE) support
- Multilevel shadowing on XCMP
Six Enhanced Capture (eCAP) modules
- High-resolution Capture (HRCAP) available on two of the six eCAP modules
- Two new monitor units for edge, pulse width and period that can be coupled with ePWM strobes and trip events
- Increased 256 multiplexed capture inputs
- New ADC SOC generation capability
Six Enhanced Quadrature Encoder Pulse (eQEP) modules
16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
Embedded Pattern Generator (EPG)
Configurable Logic Block (CLB)
- Six tiles
- Augments existing peripheral capability
- Supports position manager solutions

Communications Peripherals

EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
Fast Serial Interface (FSI) with four transmitters and four receivers
Five high-speed (up to 50MHz) SPI ports (pin-bootable)
Six High-Speed Universal Asynchronous Receiver/Transmitters (UARTs) (pin-bootable)
Two I2C interfaces (pin-bootable)
Two Local Interconnect Network (LIN) (supports SCI)
Power-Management Bus (PMBus) interface (supports I2C)
Six Single Edge Nibble Transmission interface (SENT)
Six Controller Area Networks with Flexible Data Rate (CAN FD/MCAN) (pin-bootable)

Systems Peripherals

External Memory Interface (EMIF) with ASRAM and SDRAM support
Two 10-channel Real-Time Direct Memory Access (RTDMA) controllers with MPU
Up to 190 usable signal pins
- 136 General-Purpose Input/Output (GPIO) pins
- 80 analog pins (26 AGPIOs included in GPIOs)
Peripheral Interrupt Priority and Expansion (PIPE)
Low-power mode (LPM) support
Embedded Real-time Analysis and Diagnostic (ERAD)

Clock and System Control

On-chip crystal oscillator
Windowed watchdog timer module
Missing clock detection circuitry
1.2V core, 3.3V I/O design
- Internal VREG for 1.2V generation
- Brownout reset (BOR) circuit

Package Options:

Lead-free, green packaging
256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEX suffix], 13mm x 13mm/0.8mm pitch
176-pin Thermally Enhanced Thin Quad Flatpack (HTQFP) [PTS suffix], 22mm x 22mm/0.4mm pitch
144-pin HTQFP [RFS suffix],18mm x 18mm/0.4mm pitch
100-pin HTQFP [PZS suffix],14mm x 14mm/0.4mm pitch

Temperature

Ambient (TA): –40°C to 125°C

The F29H85x and F29P58x are members of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of GaN and SiC technologies.

These include such applications as:

The real-time control subsystem has up to three 200MHz C29x DSP cores. The C29x supports 32-bit and 64-bit floating- and fixed-point signal-processing running from on-chip flash or RAM. The C29x CPU is boosted by trigonometric math instructions, speeding up common algorithms key to real-time control systems.

Many features are included to support a system-level ASIL-D functional safety solution. The C29x CPU1 and CPU2 cores can be put in lockstep for detection of permanent and transient faults. Logic Power-On Self-Test (LPOST) and Memory Power-On Self-Test (MPOST) provide start-up detection of latent faults. Safe interconnects provide fault detection between the CPU and the peripherals. The ADC safety checker compares ADC conversion results from multiple ADC modules without additional CPU cycles. The Waveform Analyzer and Diagnostic (WADI) can monitor multiple signals for proper operation and take action to ensure a safe state is maintained. The device architecture features a Safe Interconnect (SIC) for end-to-end code and data safety, with CPU-based ECC protection for all memories and peripheral endpoints.

Hardware Security Manager (HSM) provides EVITA-full security support. Features include Secure Boot, secure storage and keyring support, secure debug authentication, and cryptographic accelerator engines. The HSM enables secure key and code provisioning in untrusted factory environments, and supports Firmware-Over-The-Air updates of HSM and host application firmware, with A/B swap capability and rollback control.

SSU (Safety and Security unit) enables superior run-time safety and security features. This feature can be used create safety isolation (Freedom From Interference) among the threads running on same CPU or different CPUs. The SSU features a context-sensitive MPU mechanism that automatically switches access permissions in hardware based on currently executing thread or task. This eliminates software overhead, enabling real-time code performance without compromising system safety. The SSU provides multi-user debug authentication, and also supports Live Firmware Update (LFU) and FOTA fpr application firmware updates with A/B swap and rollback control.

High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. Two 16-bit Analog-to-Digital Converters (ADC) and three 12-bit ADCs have up to 80 analog channels as well as an integrated post-processing block and hardware oversampling. Two 12-bit buffered DACs and twenty-four comparator channels are available.

Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL), Diode Emulation (DE), and Illegal Combo Logic (ICL) features.

The Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU.

An EtherCAT SubDevice Controller, Ethernet MAC, and other industry-standard protocols like CAN FD are available on this device. The Fast Serial Interface (FSI) enables up to 200Mbps of robust communications across an isolation boundary.

Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000 real-time microcontrollers page.

The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered.

Ready to get started? Check out the F29H85X-SOM-EVM evaluation board, and download the MCU-SDK-F29H85x software development kit.