UCC20225A-Q1
- AEC Q100 qualified with:
- Device temperature grade 1
- Device HBM ESD classification level H2
- Device CDM ESD classification level C6
- Single PWM input, dual output
- Resistor-programmable dead time
- 4-A peak source, 6-A peak sink output
- CMTI greater than 100-V/ns
- Switching parameters:
- 19-ns typical propagation delay
- 5-ns maximum delay matching
- 6-ns maximum pulse-width distortion
- 3-V to 18-V input VCCI range
- Up to 25-V VDD with 5V and 8-V UVLO Options
- Rejects input transients shorter than 5-ns
- TTL and CMOS compatible inputs
- 5-mm x 5-mm space-saving LGA-13 Package
- Safety-related certifications:
- 3535-VPK isolation per VDE V 0884-11:2017
- 2500-VRMS isolation for 1 minute per UL 1577
- CQC Certification per GB4943.1-2011
The UCC20225-Q1 family are single-input, dual-output isolated gate drivers with 4-A source and 6-A sink peak current in 5-mm x 5-mm LGA-13. It is designed to drive power transistors up to 5-MHz with best-in-class propagation delay and pulse-width distortion.
The input side is isolated from the two output drivers by a 2.5-kVRMS isolation barrier, with minimum 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two output-side drivers allows working voltage up to 700-VDC.
The UCC20225-Q1 family allow programmable dead time through a resistor on DT pin. A DIS pin shuts down both outputs simultaneously when set high, and allows normal operation when left grounded.
The device accepts VDD supply voltages up to 25-V. A wide VCCI range from 3-V to 18-V makes the driver suitable for interfacing with both analog and digital controllers. All supply voltage pins have under voltage lock-out (UVLO) protection.
With all these advanced features, the UCC20225-Q1 family enables high power density, high efficiency, and robustness in a variety of automotive applications.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | UCC20225-Q1, UCC20225A-Q1 Isolated Dual-Channel Gate Driver with Single Input in LGA for Automotive 48-V Systems datasheet (Rev. C) | PDF | HTML | 2019/09/19 |
| White paper | Understanding failure modes in isolators (Rev. B) | PDF | HTML | 2024/01/29 | |
| Analog Design Journal | Why use PSR‐flyback isolated converters in dual‐battery mHEV systems (Rev. A) | PDF | HTML | 2023/05/25 | |
| Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020/02/28 | ||
| Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020/02/28 | ||
| White paper | Driving the future of HEV/EV with high-voltage solutions (Rev. B) | 2018/05/16 | ||
| White paper | Cities grow smarter through innovative semiconductor technologies | 2017/07/07 |
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VLGA (NPL) | 13 | Ultra Librarian |
주문 및 품질
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- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
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