DP83865
- Ultra low power consumption typically 1.1 watt
- Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
- Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
- 3.3V or 2.5V MAC interfaces:
- IEEE 802.3u MII
- IEEE 802.3z GMII
- RGMII version 1.3
- User programmable GMII pin ordering
- IEEE 802.3u Auto-Negotiation and Parallel Detection
- Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
- Speed Fallback mode to achieve quality link
- Cable length estimator
- LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
- Supports 25 MHz operation with crystal or oscillator.
- Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
- User programable interrupt
- Supports Auto-MDIX at 10, 100 and 1000 Mb/s
- Supports JTAG (IEEE1149.1)
- 128-pin PQFP package (14mm x 20mm)
The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.
The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).
The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer datasheet (Rev. B) | 2007年 12月 11日 | |
Application note | AN-1511 Cable Discharge Event (Rev. A) | 2013年 4月 26日 | ||
Application note | DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer Design Guide (Rev. D) | 2013年 4月 26日 | ||
Application note | DP83865/864 Gigabit Physical Layer Device Trouble Shooting Guide (Rev. A) | 2013年 4月 26日 | ||
Application note | Dual Foot Print Layout Notes for DP83865 Gig PHYTER V & DP83847 DS PHYTER II (Rev. A) | 2013年 4月 26日 | ||
Application brief | PhyworkX Ethernet PHY Development Kit | 2012年 2月 27日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ETHERNET-SW — 乙太網路 PHY Linux 驅動程式和工具
USB-2-MDIO 軟體可讓您在偵錯和原型設計期間直接存取暫存器。 此工具支援所有 TI 乙太網路 PHY。
啓用驅動程式支援
使用 "make menuconfig" 配置核心 (或者使用 "make xconfig" 或 "make nconfig")
Menuconfig 位置
//在下例中更改符號欄位以和零件編號
符號相符:DP83848_PHY [=y]
類型:tristate
提示:適用於德州儀器 DP83848 PHY
(...)
USB-2-MDIO — USB-2-MDIO Tool v1.0
The USB-2-MDIO software tool lets Texas Instruments' Ethernet PHYs access the MDIO status and device control registers. The USB-2-MDIO tool includes a LaunchPad™ Development kit for TI's MSP430™ MCUs that is interfaced with a lightweight GUI. The (...)
支援產品和硬體
產品
乙太網路 PHY
硬體開發
開發板
開發套件
軟體
驅動程式或資料庫
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
QFP (NND) | 128 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點