DS125DF1610
- Pin-Compatible Family
- DS150DF1610: 12.5 to 15 G
- DS125DF1610: 9.8 to 12.5 G
- DS110DF1610: 8.5 to 11.3 G
- 4x4 Analog Cross Point Switch for Each Quad
- Fully Adaptive CTLE
- Self tuning DFE, with Optional Continuous Adaption
- Configurable VGA
- Adjustable Transmit VOD
- Adjustable 3-tap Transmit FIR Filter
- On-chip AC Coupling on Receive Inputs
- Locks to Half/Quarter/Eighth Data Rates for Legacy Support
- On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator
- Supports JTAG Boundary Scan
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection
- Single 2.5 V ±5% Power Supply
- SMBus Based Register Configuration
- Optional EEPROM Configuration
- 15 mm × 15 mm, 196-pin FCBGA Package
- Operating Temp Range : –40°C to +85°C
The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS125DF1610 9.8 to 12.5 Gbps 16-Channel Retimer datasheet (Rev. B) | PDF | HTML | 2017年 1月 13日 |
| Application note | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023年 1月 31日 | ||
| EVM User's guide | DS125DF1610EVM User's Guide (Rev. B) | 2018年 9月 20日 | ||
| Technical article | Eye doctor: Reflections and how to deal with them in high-speed systems | PDF | HTML | 2016年 9月 8日 | |
| Analog Design Journal | Green box testing: A method for optimizing high-speed serial links | 2016年 7月 21日 | ||
| Application note | Understanding EEPROM Programming for 10G to 12.5G Retimers | 2016年 1月 13日 | ||
| Application note | Selecting TI SigCon Devices for SFF-8431 SFP+ Applications | 2014年 5月 6日 |
設計與開發
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DS125DF1610EVM — 9.8 至 12.5 Gbps 16 通道重定時器評估模組
The DS125DF1610EVM allows for easy evaluation of the DS125DF1610. Users are required to supply power and high speed traffic to the EVM via the SMA connectors. A low cost on board oscillator provides a reference clock for the DS125DF1610’s PPM counter, so external clocking equipment is not (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TIDA-00426 — 12 Gbps 多通道 BERT 板參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ABB) | 196 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。