TPS51100

現行

3A 源極/汲極 DDR 終端器穩壓器

產品詳細資料

Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
HVSSOP (DGQ) 10 14.7 mm² 3 x 4.9
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 6
類型 標題 日期
* Data sheet TPS51100 3-A Sink / Source DDR Termination Regulator datasheet (Rev. E) PDF | HTML 2014年 12月 17日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日
Selection guide Power Management Guide 2018 (Rev. R) 2018年 6月 25日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
User guide Using the TPS51100 2004年 7月 13日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TPS51116EVM-001 — TPS51116 記憶體功率解決方案,同步降壓控制器評估模組

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

使用指南: PDF
TI.com 無法提供
模擬型號

TPS51100 PSpice Model

SLVC176.ZIP (473 KB) - PSpice Model
模擬型號

TPS51100 TINA-TI Average Reference Design

SLVC203.ZIP (217 KB) - TINA-TI Reference Design
模擬型號

TPS51100 TINA-TI Average Sink Reference Design (Rev. A)

SLVC177A.ZIP (217 KB) - TINA-TI Reference Design
模擬型號

TPS51100 TINA-TI Average Spice Model

SLVC204.ZIP (7 KB) - TINA-TI Spice Model
模擬型號

TPS51100 TINA-TI Transient Reference Design

SLVC206.ZIP (216 KB) - TINA-TI Reference Design
模擬型號

TPS51100 TINA-TI Transient Spice Model

SLVC205.ZIP (7 KB) - TINA-TI Spice Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HVSSOP (DGQ) 10 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片