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AC/DC 和 DC/DC 轉換器 (整合式 FET)

TPS54824

現行

採用 HotRod™ QFN 的 4.5-V 至 17-V、8-A 同步 SWIFT™ 降壓轉換器

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產品規格表

TPS54824

現行
產品規格表 立即訂購

產品詳細資料

Rating Catalog Operating temperature range (°C) -40 to 150 Topology Buck Type Converter Iout (max) (A) 8 Vin (min) (V) 4.5 Vin (max) (V) 17 Switching frequency (min) (kHz) 200 Switching frequency (max) (kHz) 1600 Features Enable, Frequency synchronization, Power good, Pre-Bias Start-Up, Soft Start Adjustable, Synchronous Rectification, Tracking Control mode current mode Vout (min) (V) 0.6 Vout (max) (V) 12 Iq (typ) (µA) 580 Duty cycle (max) (%) 98
Rating Catalog Operating temperature range (°C) -40 to 150 Topology Buck Type Converter Iout (max) (A) 8 Vin (min) (V) 4.5 Vin (max) (V) 17 Switching frequency (min) (kHz) 200 Switching frequency (max) (kHz) 1600 Features Enable, Frequency synchronization, Power good, Pre-Bias Start-Up, Soft Start Adjustable, Synchronous Rectification, Tracking Control mode current mode Vout (min) (V) 0.6 Vout (max) (V) 12 Iq (typ) (µA) 580 Duty cycle (max) (%) 98
VQFN-HR (RNV) 18 12.25 mm² 3.5 x 3.5
  • Small 3.5-mm × 3.5-mm HotRod™ QFN package
  • Integrated 14.1-mΩ and 6.1-mΩ MOSFETs
  • Peak current mode control with fast transient response
  • 200-kHz to 1.6-MHz fixed switching frequency
  • Synchronizes to external clock
  • 0.6-V voltage reference ±0.85% over temperature
  • 0.6-V to 12-V output voltage range
  • Hiccup Current Limit
  • Safe start-up into pre-biased output voltage
  • Adjustable soft start and power sequencing
  • Adjustable input undervoltage lockout
  • 3-µA shutdown current
  • Power good output monitor for undervoltage and overvoltage
  • Output overvoltage protection
  • Non-latch thermal shutdown protection
  • –40°C to 150°C operating junction temperature
  • Small 3.5-mm × 3.5-mm HotRod™ QFN package
  • Integrated 14.1-mΩ and 6.1-mΩ MOSFETs
  • Peak current mode control with fast transient response
  • 200-kHz to 1.6-MHz fixed switching frequency
  • Synchronizes to external clock
  • 0.6-V voltage reference ±0.85% over temperature
  • 0.6-V to 12-V output voltage range
  • Hiccup Current Limit
  • Safe start-up into pre-biased output voltage
  • Adjustable soft start and power sequencing
  • Adjustable input undervoltage lockout
  • 3-µA shutdown current
  • Power good output monitor for undervoltage and overvoltage
  • Output overvoltage protection
  • Non-latch thermal shutdown protection
  • –40°C to 150°C operating junction temperature

The TPS54824 is a full-featured 17-V (19-V maximum), 8-A synchronous step-down DC/DC converter in a 3.5 mm × 3.5 mm HotRod™ QFN package.

The device is optimized for small solution size through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through peak current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor footprint.

The peak current mode control simplifies the loop compensation and provides fast transient response. Cycle-by-cycle peak current limiting on the high-side and low-side sourcing current limit protects the device in overload situations. Hiccup limits MOSFET power dissipation if a short circuit or over loading fault persists.

A power good supervisor circuit monitors the regulator output. The PGOOD pin is an open-drain output and goes high impedance when the output voltage is in regulation. An internal deglitch time prevents the PGOOD pin from pulling low unless a fault has occurred.

A dedicated EN pin can be used to control the regulator on/off and adjust the input undervoltage lockout. The output voltage start-up ramp is controlled by the SS/TRK pin, which allows operation as either a standalone power supply or in tracking situations.

The TPS54824 is a full-featured 17-V (19-V maximum), 8-A synchronous step-down DC/DC converter in a 3.5 mm × 3.5 mm HotRod™ QFN package.

The device is optimized for small solution size through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through peak current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor footprint.

The peak current mode control simplifies the loop compensation and provides fast transient response. Cycle-by-cycle peak current limiting on the high-side and low-side sourcing current limit protects the device in overload situations. Hiccup limits MOSFET power dissipation if a short circuit or over loading fault persists.

A power good supervisor circuit monitors the regulator output. The PGOOD pin is an open-drain output and goes high impedance when the output voltage is in regulation. An internal deglitch time prevents the PGOOD pin from pulling low unless a fault has occurred.

A dedicated EN pin can be used to control the regulator on/off and adjust the input undervoltage lockout. The output voltage start-up ramp is controlled by the SS/TRK pin, which allows operation as either a standalone power supply or in tracking situations.
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技術文件

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類型 標題 日期
* Data sheet TPS54824 4.5-V to 17-V (19-V Maximum) Input, 8-A Synchronous SWIFT™ Step-Down Converter datasheet (Rev. B) PDF | HTML 2019年 10月 17日
Application note Peak Current Mode Converter Secondary Stage Filter Design for Low Ripple Power – Part I: Filter Design for Out PDF | HTML 2024年 2月 27日
Application note Peak Current Mode Converter Secondary Stage Filter Design for Low Ripple Power – Part II: Hybrid Sense Network PDF | HTML 2024年 2月 27日
Application note Collection of DC/DC Buck Regulator Technical Documentation (Rev. A) PDF | HTML 2022年 11月 28日
EVM User's guide TPS54824 SWIFT™ Step-Down Converter Evaluation Module User's Guide (Rev. B) PDF | HTML 2021年 8月 19日
Application note DC/DC Converter Solutions for Hardware Accelerators in Data Center Applications (Rev. A) PDF | HTML 2021年 5月 4日
Application note Non-Isolated Point-of-Load Solutions for Tiger Lake in PC Applications (Rev. B) PDF | HTML 2021年 4月 29日
Selection guide Buck Converter Quick Reference Guide (Rev. B) 2021年 4月 8日
Application note Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) PDF | HTML 2020年 1月 8日
Application note Understanding Flip Chip QFN (HotRod) and Standard QFN Performance Differences 2019年 7月 2日
Application note Minimizing Output Ripple During Startup (Rev. A) 2019年 5月 20日
Application note DC/DC Point-of-load Power Solutions for Wired Networking Switch Systems 2018年 12月 11日
Application note Optimizing Layout of the TPS54824 HotRod™ Package for Thermal Performance 2018年 11月 16日
Application note Solve Point-of-Load Power Design Challenges: Single Board Computer Applications 2018年 8月 24日
Application note Create an Inverting Power Supply Using a Synchronous Step-Down Regulator (Rev. B) 2018年 6月 25日
More literature Common Mistakes in DC/DC Converters and How to Fix Them 2018年 2月 14日
White paper Measuring various types of low-frequency noise in DC/DC switching converters 2018年 2月 1日
Analog Design Journal Reducing noise on the output of a switching regulator 2018年 1月 4日
Application note Minimizing Output Ripple During Startup 2017年 6月 22日
Application note HotRod QFN Application Note 2014年 4月 9日
Application note Ultra Small 5A, Adjustable Output Reference design using TPS54620 2010年 5月 21日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TPS54824EVM-779 — TPS54824 同步降壓轉換器評估模組

The TPS54824EVM-779 is a 8 A synchronous converter evaluation module (EVM).  The EVM generates a 1.8 V output voltage from a nominal 12 V input.  The input voltage range is 4.5 V to 17 V.  The circuit is set up for operation at 700 kHz.
使用指南: PDF | HTML
TI.com 無法提供
模擬型號

TPS54824 PSpice Average Model (Rev. C)

SLVMBY0C.ZIP (57 KB) - PSpice Model
下載
模擬型號

TPS54824 PSpice Transient Model (Rev. B)

SLVMBU2B.ZIP (236 KB) - PSpice Model
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模擬型號

TPS54824 TINA-TI Average Reference Design (Rev. C)

SLVMBZ3C.TSC (153 KB) - TINA-TI Reference Design
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模擬型號

TPS54824 TINA-TI Average Spice Model (Rev. C)

SLVMBZ4C.ZIP (9 KB) - TINA-TI Spice Model
下載
參考設計

TIDA-01466 — 適用於超音波前端的低電壓、低雜訊電源參考設計

This reference design is a power supply optimized specifically for providing power to eight 16-channel receive AFE ICs for ultrasound imaging systems. This design reduces part count while maximizing efficiency by using single-chip DC-DC converter + LDO combo regulators to set the LDO input just (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01510 — 配備 DC/DC 轉換器且可提高功率密度的雙面佈線圖參考設計

This reference design demonstrates the correct way to design a two-sided DC/DC layout in an effort to achieve higher power-supply density. The design guide highlights common mistakes and how to avoid them, along with test results showing that proper implemenation of the TPS54824 device in a (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN-HR (RNV) 18 Ultra Librarian
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