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線性與低壓差 (LDO) 穩壓器

TPS7A80

現行

具有低 IQ 和啟用功能的 1A、高 PSRR、超低壓差電壓穩壓器

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TLV759P 現行 具有啟用功能的 1A、低 IQ、高準確度、可調整超低壓差電壓穩壓器 1-A single-channel adjustable-output LDO regulator with lower IQ for cost-sensitive applications.
TPS7A88 現行 1-A、低雜訊、高 PSRR、雙通道可調式超低壓降電壓穩壓器 Dual-channel, low-noise, 1-A LDO regulator.
TPS7A91 現行 具高準確度的 1-A、低雜訊、高 PSRR、可調式超低壓降電壓穩壓器 Next-generation product with lower noise and lower dropout.

TPS7A80

現行
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產品詳細資料

Output options Adjustable Output, Fixed Output Iout (max) (A) 1 Vin (max) (V) 6.5 Vin (min) (V) 2.2 Vout (max) (V) 6 Vout (min) (V) 0.8 Fixed output options (V) 1.2, 1.8, 3.3, 5 Rating Catalog Noise (µVrms) 50 PSRR at 100 KHz (dB) 57 Iq (typ) (mA) 0.06 Thermal resistance θJA (°C/W) 48 Load capacitance (min) (µF) 4.7 Regulated outputs (#) 1 Features Enable Accuracy (%) 3 Dropout voltage (Vdo) (typ) (mV) 170 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 1 Vin (max) (V) 6.5 Vin (min) (V) 2.2 Vout (max) (V) 6 Vout (min) (V) 0.8 Fixed output options (V) 1.2, 1.8, 3.3, 5 Rating Catalog Noise (µVrms) 50 PSRR at 100 KHz (dB) 57 Iq (typ) (mA) 0.06 Thermal resistance θJA (°C/W) 48 Load capacitance (min) (µF) 4.7 Regulated outputs (#) 1 Features Enable Accuracy (%) 3 Dropout voltage (Vdo) (typ) (mV) 170 Operating temperature range (°C) -40 to 125
VSON (DRB) 8 9 mm² 3 x 3
  • Low-Dropout 1-A Regulator With Enable
  • Adjustable Output Voltages: 0.8 V to 6 V
  • Fixed Output Voltages: 0.8 V to 6 V
  • Wide-Bandwidth High PSRR:
    • 63 dB at 1 kHz
    • 57 dB at 100 kHz
    • 38 dB at 1 MHz
  • Low Noise: (14 × VOUT ) µVRMS Typical (100 Hz to 100 kHz)
  • Stable with a 4.7-µF Ceramic Capacitor
  • Excellent Load/Line Transient Response
  • 3% Overall Accuracy (Over Load/Line/Temp)
  • Overcurrent and Overtemperature Protection
  • Very Low Dropout: 170 mV Typical at 1 A
  • 3-mm × 3-mm VSON-8 DRB Package
  • Low-Dropout 1-A Regulator With Enable
  • Adjustable Output Voltages: 0.8 V to 6 V
  • Fixed Output Voltages: 0.8 V to 6 V
  • Wide-Bandwidth High PSRR:
    • 63 dB at 1 kHz
    • 57 dB at 100 kHz
    • 38 dB at 1 MHz
  • Low Noise: (14 × VOUT ) µVRMS Typical (100 Hz to 100 kHz)
  • Stable with a 4.7-µF Ceramic Capacitor
  • Excellent Load/Line Transient Response
  • 3% Overall Accuracy (Over Load/Line/Temp)
  • Overcurrent and Overtemperature Protection
  • Very Low Dropout: 170 mV Typical at 1 A
  • 3-mm × 3-mm VSON-8 DRB Package

The TPS7A80 family of low-dropout linear regulators (LDOs) offer very high power-supply ripple rejection (PSRR) at the output. This LDO family uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.

The TPS7A80 family is stable with a 4.7-µF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.

This family is fully specified over the temperature range of TJ = –40°C to +125°C, and is offered in a 3-mm × 3-mm, VSON-8 package with a thermal pad.

The TPS7A80 family of low-dropout linear regulators (LDOs) offer very high power-supply ripple rejection (PSRR) at the output. This LDO family uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.

The TPS7A80 family is stable with a 4.7-µF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.

This family is fully specified over the temperature range of TJ = –40°C to +125°C, and is offered in a 3-mm × 3-mm, VSON-8 package with a thermal pad.
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類型 標題 日期
* Data sheet TPS7A80 Low-Noise, Wide-Bandwidth, High PSRR, Low-Dropout 1-A Linear Regulator datasheet (Rev. J) PDF | HTML 2018年 1月 18日
White paper Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022年 12月 14日
White paper Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022年 12月 13日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 2018年 3月 21日
User guide TSW2200 Multi-Output Power Supply Board (Rev. A) 2012年 12月 13日
Application note LDO Performance Near Dropout 2010年 10月 8日
EVM User's guide TPS7A80xxDRBEVM User's Guide 2010年 7月 14日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

LMK03318EVM — 具有 1 個 PLL、8 個差動輸出和 2 個輸入的 LMK03318EVM 超低抖動時鐘產生器 EVM

The LMK03318EVM evaluation module provides a complete clocking platform to evaluate the 100-fs RMS jitter performance and pin-/software-configuration modes and features of the Texas Instruments LMK03318 Ultra-Low-Jitter Clock Generator with 1 PLL, 8 outputs, 2 inputs, and integrated EEPROM.

The (...)

使用指南: PDF
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開發板

LMK03328EVM — 具有 2 個 PLL、8 個差動輸出和 2 個輸入的 LMK03328EVM 超低抖動時鐘產生器 EVM

The LMK03328EVM evaluation module provides a complete clocking platform to evaluate the 100-fs RMS jitter performance and pin-/software-configuration modes and features of the Texas Instruments LMK03328 Ultra-Low-Jitter Clock Generator with Dual PLLs, 8 outputs, 2 inputs, and integrated EEPROM.

The (...)

使用指南: PDF
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開發板

TPS7A8001DRBEVM — TPS7A8001 低雜訊、高頻寬 PSRR、1A LDO 線性穩壓器評估模組

The TPS7A8001DRBEVM is a fully assembled and tested circuit for evaluating the TPS7A8001 Low-Noise, High-Bandwidth PSRR, Low-Dropout 1A Linear Regulator in the DRB (3mm x 3mm SON-8) package.
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模擬型號

TPS7A8001 PSpice Transient Model (Rev. A)

SBVM298A.ZIP (23 KB) - PSpice Model
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TPS7A8001 Unencrypted PSpice Transient Model

SBVM880.ZIP (1 KB) - PSpice Model
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TPS7A8012 PSpice Transient Model

SBVM884.ZIP (40 KB) - PSpice Model
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TPS7A8012 Unencrypted PSpice Transient Model

SBVM888.ZIP (2 KB) - PSpice Model
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TPS7A8018 PSpice Transient Model

SBVM890.ZIP (40 KB) - PSpice Model
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TPS7A8018 Unencrypted PSpice Transient Model

SBVM886.ZIP (2 KB) - PSpice Model
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TPS7A8033 PSpice Transient Model

SBVM883.ZIP (40 KB) - PSpice Model
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TPS7A8033 Unencrypted PSpice Transient Model

SBVM887.ZIP (2 KB) - PSpice Model
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TPS7A8050 PSpice Transient Model

SBVM889.ZIP (40 KB) - PSpice Model
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TPS7A8050 Unencrypted PSpice Transient Model

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參考設計

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Design guide: PDF
電路圖: PDF
參考設計

TIDA-00507 — 適用於微伺服器之 Intel Atom C2000 SoC VCCP 和 VNN 軌的高功率密度 9 至 15V 參考設計

The TI TPS53625 VR12 reference design (TIDA-00507), supporting Intel® Atom™ C2000, uses TI's driverless PWM architecture with TI power stages for high power density, high efficiency, and low component count while meeting Intel voltage tolerance requirements with low ripple and high (...)
Test report: PDF
電路圖: PDF
參考設計

TIDA-00094 — 具有可變增益放大器的四通道 250-Msps 數位器參考設計

This reference design shows a quad channel, 14-bit, 250-Msps digitizer with wide input range using the LMH6881 programmable differential amplifier and ADS4449 quad-channel, 14-bit, 250-Msps ADC. This combination allows an input voltage range of approximately 1 Vpp to 100 uVpp (4 dBm to -75 dBm) (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00093 — 最佳化 THS4509 以驅動高速 ADC 參考設計

This reference design shows the ability of the high-speed amplifier, THS4509 to perform single-ended to differential conversion to drive high-speed analog-to-digital converters (ADCs) while maintaining excellent noise and distortion performance. Performance versus input frequency is shown for both (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00076 — 相鄰通道功率比 (ACPR) 和誤差向量幅度 (%EVM) 量測

This reference design discusses the use of the TSW3085EVM with the TSW3100 pattern generator to test adjacent channel power ratio (ACPR) and error vector magnitude (EVM) measurements of LTE baseband signals. By using the TSW3100 LTE GUI, patterns are loaded into the TSW3085EVM which is comprised of (...)
使用指南: PDF
電路圖: PDF
參考設計

TIDA-00092 — 將 LMH6554 最佳化以驅動高速 ADC

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Design guide: PDF
電路圖: PDF
參考設計

TIDA-00074 — 寬頻射頻轉數位複雜接收器 - 回饋訊號鏈

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Design guide: PDF
電路圖: PDF
參考設計

TIDA-00068 — 具有 DPD 回饋路徑的基地台收發器

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電路圖: PDF
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