首頁 電源管理 閘極驅動器 低壓側驅動器
首頁
電源管理
閘極驅動器
低壓側驅動器

UCC27512-EP

現行

採 SON 封裝且具 5-V UVLO 的強化型產品 4-A/8-A 單通道閘極驅動器

立即訂購
產品規格表

UCC27512-EP

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 8 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Hysteretic Logic Operating temperature range (°C) -55 to 125 Rise time (ns) 9 Fall time (ns) 7 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating HiRel Enhanced Product Undervoltage lockout (typ) (V) 4 Driver configuration Inverting, Non-Inverting
Number of channels 1 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 8 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Hysteretic Logic Operating temperature range (°C) -55 to 125 Rise time (ns) 9 Fall time (ns) 7 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating HiRel Enhanced Product Undervoltage lockout (typ) (V) 4 Driver configuration Inverting, Non-Inverting
WSON (DRS) 6 9 mm² 3 x 3
  • Low-Cost, Gate-Driver Device Offering Superior Replacement
    of NPN and PNP Discrete Solutions
  • 4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
  • Strong Sink Current Offers Enhanced Immunity Against Miller Turn On
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (9-ns and 7-ns typical)
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (ensures glitch free operation at
    power-up and power-down)
  • TTL and CMOS Compatible Input Logic Threshold,
    (independent of supply voltage)
  • Hysteretic Logic Thresholds for High Noise Immunity
  • Dual Input Design (choice of an inverting (IN- pin) or non-inverting
    (IN+ pin) driver configuration)
    • Unused Input Pin can be Used for Enable or Disable Function
  • Output Held Low when Input Pins are Floating
  • Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin
    Bias Supply Voltage
  • 6-Pin DRS (3mm × 3 mm WSON with exposed thermal pad) Package

Supports Defense, Aerospace, and Medical Applications

  • Controlled Baseline
  • One Assembly and Test Site
  • One Fabrication Site
  • Available in Military (–55°C to 125°C) Temperature Range
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability
  • Low-Cost, Gate-Driver Device Offering Superior Replacement
    of NPN and PNP Discrete Solutions
  • 4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
  • Strong Sink Current Offers Enhanced Immunity Against Miller Turn On
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (9-ns and 7-ns typical)
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (ensures glitch free operation at
    power-up and power-down)
  • TTL and CMOS Compatible Input Logic Threshold,
    (independent of supply voltage)
  • Hysteretic Logic Thresholds for High Noise Immunity
  • Dual Input Design (choice of an inverting (IN- pin) or non-inverting
    (IN+ pin) driver configuration)
    • Unused Input Pin can be Used for Enable or Disable Function
  • Output Held Low when Input Pins are Floating
  • Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin
    Bias Supply Voltage
  • 6-Pin DRS (3mm × 3 mm WSON with exposed thermal pad) Package

Supports Defense, Aerospace, and Medical Applications

  • Controlled Baseline
  • One Assembly and Test Site
  • One Fabrication Site
  • Available in Military (–55°C to 125°C) Temperature Range
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability

The UCC27512 single-channel, high-speed, low-side gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27512 is capable of sourcing and sinking high, peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns.

The UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turn-on effect.

UCC27512 is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of –55°C to 125°C. Internal Under Voltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best in class switching characteristics, is especially suited for driving emerging wide band-gap power switching devices such as GaN power semiconductor devices.

The UCC27512 single-channel, high-speed, low-side gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27512 is capable of sourcing and sinking high, peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns.

The UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turn-on effect.

UCC27512 is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of –55°C to 125°C. Internal Under Voltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best in class switching characteristics, is especially suited for driving emerging wide band-gap power switching devices such as GaN power semiconductor devices.
filter 尋找其它 低壓側驅動器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 4
類型 標題 日期
* Data sheet Single Channel High-Speed, Low-Side Gate Driver (With 4-A/8-A Peak Source/Sink). datasheet 2013年 6月 10日
* Radiation & reliability report UCC27512MDRSTEP Reliability Report 2016年 2月 9日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
WSON (DRS) 6 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片