DS90C241

Name: DS90C241
Brand: TI
SKU: DS90C241
Price: 4.9 USD

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5-MHz bis 35-MHz DC-symmetrischer 24-Bit FPD-Link II Serializer

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Datenblatt

document-pdfAcrobat DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer datasheet (Rev. M) (Englisch) PDF | HTML

DS90C241

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Datenblatt

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Produktdetails

Function

Serializer

Color depth (bpp)

18

Input compatibility

LVCMOS

Output compatibility

FPD-Link LVDS

Features

Low-EMI Point-to-Point Communication

Applications

Advanced Driver Assistance Systems (ADAS)

Rating

Catalog

Operating temperature range (°C)

-40 to 105

Function

Serializer

Color depth (bpp)

18

Input compatibility

LVCMOS

Output compatibility

FPD-Link LVDS

Features

Low-EMI Point-to-Point Communication

Applications

Advanced Driver Assistance Systems (ADAS)

Rating

Catalog

Operating temperature range (°C)

-40 to 105

TQFP (PFB)

48

81 mm² 9 x 9

5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
Individual Power-Down Controls for Both Transmitter and Receiver
Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
LOCK Output Flag to Ensure Data Integrity at Receiver Side
Balanced T_SETUP and T_HOLD Between RCLK and RDATA on Receiver Side
PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
All LVCMOS Inputs and Control Pins Have Internal Pulldown
On-Chip Filters for PLLs on Transmitter and Receiver
Temperature Range: –40°C to 105°C
Greater Than 8-kV HBM ESD Tolerant
Meets AEC-Q100 Compliance
Power Supply Range: 3.3 V ± 10%
48-Pin TQFP Package

5-MHz to 35-MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
User Defined Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive Up to 10-Meter Shielded Twisted-Pair Cable
User-Selectable Clock Edge for Parallel Data on Both Transmitter and Receiver
Internal DC Balancing Encode and Decode (Supports AC-Coupling Interface With No External Coding Required)
Individual Power-Down Controls for Both Transmitter and Receiver
Embedded Clock CDR (Clock and Data Recovery) on Receiver and No External Source of Reference Clock Required
All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
LOCK Output Flag to Ensure Data Integrity at Receiver Side
Balanced T_SETUP and T_HOLD Between RCLK and RDATA on Receiver Side
PTO (Progressive Turnon) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
All LVCMOS Inputs and Control Pins Have Internal Pulldown
On-Chip Filters for PLLs on Transmitter and Receiver
Temperature Range: –40°C to 105°C
Greater Than 8-kV HBM ESD Tolerant
Meets AEC-Q100 Compliance
Power Supply Range: 3.3 V ± 10%
48-Pin TQFP Package

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.

The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.

The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.

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Andere Serializer/Deserializer für FPD-Link suchen

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Alle anzeigen 6

	Typ	Titel		Datum
*	Data sheet	DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer datasheet (Rev. M)	PDF \| HTML	03 Jan 2017
	Application note	LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)		29 Apr 2013
	Application note	Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)		26 Apr 2013
	User guide	SERDES24-35OVT Evaluation Kit for OV7710 Image Sensor Application w/ a FPD-Link		23 Feb 2012
	User guide	DS90C241/DS90C124 FPD- Link II Embedded Clock LVDS SerDes EVK User Guide		26 Jan 2012
	User guide	DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide		26 Jan 2012

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DS90C241

5-MHz bis 35-MHz DC-symmetrischer 24-Bit FPD-Link II Serializer

DS90C241

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