Startseite Schnittstelle Highspeed-Serializer/Deserializer Serializer/Deserializer für FPD-Link

DS90CF364

AKTIV

LVDS-Empfänger, 18-Bit-Flachbildschirm (FPD)-Link, +3,3V – 65 MHz

Produktdetails

Function Deserializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Deserializer Color depth (bpp) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 20 to 65 MHz shift clock support
  • Programmable Transmitter (DS90C363) strobe select (Rising or Falling edge strobe)
  • Single 3.3V supply
  • Chipset (TX + RX) power consumption < 250 mW (typ)
  • Power-down mode (< 0.5 mW total)
  • Single pixel per clock XGA (1024×768) ready
  • Supports VGA, SVGA, XGA and higher addressability
  • Up to 170 Megabyte/sec bandwidth
  • Up to 1.3 Gbps throughput
  • Narrow bus reduces cable size and cost
  • 290 mV swing LVDS devices for low EMI
  • PLL requires no external components
  • Low profile 48-lead TSSOP package
  • Falling edge data strobe Receiver
  • Compatible with TIA/EIA-644 LVDS standard
  • ESD rating > 7 kV
  • Operating Temperature: −40°C to +85°C

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

  • 20 to 65 MHz shift clock support
  • Programmable Transmitter (DS90C363) strobe select (Rising or Falling edge strobe)
  • Single 3.3V supply
  • Chipset (TX + RX) power consumption < 250 mW (typ)
  • Power-down mode (< 0.5 mW total)
  • Single pixel per clock XGA (1024×768) ready
  • Supports VGA, SVGA, XGA and higher addressability
  • Up to 170 Megabyte/sec bandwidth
  • Up to 1.3 Gbps throughput
  • Narrow bus reduces cable size and cost
  • 290 mV swing LVDS devices for low EMI
  • PLL requires no external components
  • Low profile 48-lead TSSOP package
  • Falling edge data strobe Receiver
  • Compatible with TIA/EIA-644 LVDS standard
  • ESD rating > 7 kV
  • Operating Temperature: −40°C to +85°C

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF364 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbyte/sec. The Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The Transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge Transmitter will inter-operate with a Falling edge Receiver (DS90CF364) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90C363 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CF364 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbyte/sec. The Transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The Transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge Transmitter will inter-operate with a Falling edge Receiver (DS90CF364) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet DS90C363/F364 3.3V Prog LVDS Trnsmit 18Bit FPD 65MHz/LVDS Rcvr 18Bit FPD 85MHz datasheet (Rev. C) 12 Apr 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 Jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 Aug 2017
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 Jan 2016
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 Mai 2004
Application note AN-1056 STN Application Using FPD-Link 14 Mai 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 Mai 2004

Design und Entwicklung

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