Startseite Schnittstelle Highspeed-Serializer/Deserializer Serializer/Deserializer für FPD-Link

DS90UR241-Q1

AKTIV

5–43 MHz DC-symmetrischer 24-Bit FPD-Link II Serializer – für die Automobilindustrie

Produktdetails

Function Serializer Color depth (bpp) 18 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Function Serializer Color depth (bpp) 18 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
TQFP (PFB) 48 81 mm² 9 x 9
  • Supports displays with 18-bit color depth
  • 5MHz to 43MHz Pixel clock
  • Automotive-grade product AEC-Q100 grade 2 qualified
  • 24:1 Interface compression
  • Embedded clock with DC balancing supports AC-coupled data transmission
  • Capable to drive up to 10 meters shielded twisted-pair cable
  • No reference clock required (deserializer)
  • Meets ISO 10605 ESD – greater than 8kV HBM ESD structure
  • Hot plug support
  • EMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs
  • @Speed BIST (Built-In Self-Test) to validate LVDS transmission path
  • Individual power-down controls for both transmitter and receiver
  • Power supply range 3.3V ±10%
  • 48-pin TQFP package for transmitter and 64-pin TQFP package for receiver
  • Temperature range: –40°C to 105°C
  • Backward-compatible mode with DS90C241/DS90C124
  • Supports displays with 18-bit color depth
  • 5MHz to 43MHz Pixel clock
  • Automotive-grade product AEC-Q100 grade 2 qualified
  • 24:1 Interface compression
  • Embedded clock with DC balancing supports AC-coupled data transmission
  • Capable to drive up to 10 meters shielded twisted-pair cable
  • No reference clock required (deserializer)
  • Meets ISO 10605 ESD – greater than 8kV HBM ESD structure
  • Hot plug support
  • EMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs
  • @Speed BIST (Built-In Self-Test) to validate LVDS transmission path
  • Individual power-down controls for both transmitter and receiver
  • Power supply range 3.3V ±10%
  • 48-pin TQFP package for transmitter and 64-pin TQFP package for receiver
  • Temperature range: –40°C to 105°C
  • Backward-compatible mode with DS90C241/DS90C124

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet DS90URxxx-Q1 5MHz to 43MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset datasheet (Rev. P) PDF | HTML 29 Aug 2024
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 29 Apr 2013
Application note LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 29 Apr 2013
Application note AN-1807 FPD-Link II Display SerDes Overview (Rev. B) 26 Apr 2013
Application note AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B) 26 Apr 2013
Application note Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) 26 Apr 2013
User guide High Efficiency Portable Media Player (PMP) Dock Station User Guide 27 Jan 2012
User guide DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide 26 Jan 2012

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

SERDESUR-43USB — Evaluierungskit für DS90UR241 DS90UR124 Serializer- und Deserializer-Chipsatz

The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.

The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. (...)

Benutzerhandbuch: PDF
Simulationsmodell

DS90UR241 IBIS Model

SNLM026.ZIP (7 KB) - IBIS Model
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Simulationstool

TINA-TI — SPICE-basiertes analoges Simulationsprogramm

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Benutzerhandbuch: PDF
Referenzdesigns

TIDA-00137 — Referenzdesign für digitalen Video-SerDes mit WVGA-Auflösung für TFT-LCD-Fahrzeugdisplays mit DVP-Sc

The TIDA-00137 reference design is a high speed serial video interface to connect a remote automotive WVGA TFT LCD display with DVP (LVCMOS) Interface to a video processing system. It uses TIs FPD-Link II SerDes technology to transmit uncompressed video data over shielded twisted pair cable. (...)
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TQFP (PFB) 48 Ultra Librarian

Bestellen & Qualität

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  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
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  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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  • Werksstandort
  • Montagestandort

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