Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 14 |
| Betriebstemperaturbereich (°C) -55 to 125 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von SN74LV2T74-EP
- Wide operating range of 1.8 V to 5.5 V
-
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
-
Up translation:
- 1.2 V to 1.8 V
- 1.5 V to 2.5 V
- 1.8 V to 3.3 V
- 3.3 V to 5.0 V
- Down translation:
- 5.0 V, 3.3 V, 2.5 V to 1.8 V
- 5.0 V, 3.3 V to 2.5 V
- 5.0 V to 3.3 V
-
- 5.5-V tolerant input pins
- Supports standard pinouts
- Up to 150 Mbps with 5-V or 3.3-V V CC
- Latch-up performance exceeds 250 mA per JESD 17
- Supports defense, aerospace, and
medical applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
Beschreibung von SN74LV2T74-EP
The SN74LV2T74-EP contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).