DP83TC818S-Q1
- Synchronized Audio Clock Generation
- I2S & TDMx SCLK/FSYNC clock generation
- Configurable FSYNC, SCLK, MCLK frequencies
- Automatic Phase Adjustment through IEEE1722 CRF decode
- IEEE 802.1AE MACsec
- MACsec frame expansion: Inbuilt buffering and flow control support to handle 12 byte IPG ethernet frames
- Authentication, encryption at line rate
- Cipher suites: GCM-AES-XPN-128/256, GCM-AES-128/256
- Secure Channel: Total 16 SAK enabling 8 Tx/Rx SC with SAK Auto rollover support
- Ingress/Egress classification for Ethertype, VLAN, DMAC: up to 8 parallel rules
- Window replay protection
- IEEE 802.1AS time synchronization
- Highly accurate 1pps signal < ±15 ns
- Precise time stamping for MACsec encoded PTP packets
- Multiple IOs for event capture and trigger
- Robust EMC Performance
- IEC62228-5, OA EMC compliant
- SAE J2962-3 EMC compliant
- 39dBm DPI Immunity with ±5% assymetry
- <4dBµV radiated emissions in GPS and Glonass bands
- Stripline Emissions: Class-II compliant
- TC-10 compliant
- < 18µA sleep current
- Fast wake from sleep by retaining PHY configuration during sleep (optional)
- MAC Interfaces: MII, RMII Master, RGMII, SGMII
- Footprint compatible with TI’s 1000BASE-T1 PHY
- Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
- Diagnostic tool kit
- Signal Quality Indication (SQI) & Time Domain Reflectometry (TDR)
- Voltage, Temperature & ESD sensors
- PPM monitor: Provides external clock ppm drift (up to ±100 ppb accuracy)
- AEC-Q100 qualified for Automotive Applications:
- Temperature Grade 1: –40°C to +125 °C
- IEC61000-4-2 ESD level 4 MDI: ±8kV CD
The DP83TC818S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility and TC10 Sleep-Wake functionality.
The DP83TC818S-Q1 integrates IEEE802.1AS / IEEE1588v2 hardware time stamping & fractional PLL, enabling highly accurate time synchronization. The fractional PLL enables frequency and phase synchronization of the wall clock (eliminating the need for external VCXO) and generation of a wide range of time synchronized frequencies needed for audio and other ADAS applications. The PHY also integrates IEEE 1722 CRF decode to generate Media clock and Bit Clock for AVB & other audio applications.
The DP83TC818S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The DP83TC818S-Q1 supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC818S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.
The DP83TC818S-Q1 is footprint compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.
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DP83TC818EVM-MC — DP83TC818S-Q1 評估模型
DP83TC818EVM-MC 支援 100 Mbps 速度，且符合 IEEE 802.3bp 規範。板載 MSP430F5529 可與 USB2MDIO 圖形使用者介面工具搭配使用。提供 DP83867 以使用 RGMII MAC 介面支援銅線 (100BASE-TX)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
TINA-TI — 基於 SPICE 的類比模擬程式
TIDA-020071 — TDA4 四路車用 PHY RGMII 參考設計
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
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