DS250DF810
- Octal-channel multi-rate retimer with integrated signal conditioning
- All channels lock independently from 20.2752 to 25.8 Gbps (including sub-rates like 10.3125 Gbps, 12.5 Gbps, and more)
- Ultra-low latency: <500 ps typical for 25.78125 Gbps data rate
- Single power supply, no low-jitter reference clock required, and integrated ac coupling capacitors to reduce board routing complexity and BOM cost
- Integrated 2×2 cross point
- Adaptive continuous time linear equalizer (CTLE)
- Adaptive decision feedback equalizer (DFE)
- Low-jitter transmitter with 3-Tap FIR filter
- Combined equalization supporting 35+ dB channel loss at 12.9 GHz
- Adjustable transmit amplitude: 205 mVppd to 1225 mVppd (typical)
- On-chip eye opening monitor (EOM), PRBS pattern checker/generator small 8 mm × 13 mm BGA package with easy flow-through routing
- Unique pinout allows routing high-speed signals underneath the package
- Pin-compatible repeater available
The DS250DF810 is an eight-channel multi-rate Retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.
Each channel of the DS250DF810 independently locks to serial data rates in a continuous range from 20.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.3125 Gbps and 12.5 Gbps, which allows the DS250DF810 to support individual lane Forward Error Correction (FEC) pass-through.
Integrated physical AC coupling capacitors (TX and RX) eliminate the need for external capacitors on the PCB. The DS250DF810 has a single power supply and minimal need for external components. These features reduce PCB routing complexity and BOM cost.
The advanced equalization features of the DS250DF810 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is ideal for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF810 implements 2x2 cross-point on each channel pair, providing the host with both lane crossing and fanout options.
The DS250DF810 can be configured either via the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM. A non-disruptive on-chip eye monitor and a PRBS generator/checker allow for in-system diagnostics.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS250DF810 25 Gbps Multi-Rate 8-Channel Retimer datasheet (Rev. C) | PDF | HTML | 2019年 10月 24日 |
| Application note | Implementing Pin Compatible Ethernet Redrivers and Retimers | PDF | HTML | 2024年 10月 28日 | |
| Application note | Optimal Implementation of 25G-28G Ethernet Retimers versus Redrivers (Rev. B) | PDF | HTML | 2023年 5月 1日 | |
| Application note | DS2X0DF810 Junction Temperature Readback and Temperature Lock Range (TLR) Extens | PDF | HTML | 2021年 5月 24日 | |
| EVM User's guide | DS250DF810EVM User's Guide (Rev. C) | 2019年 9月 3日 | ||
| Application note | Transmitter Optimization for ≥ 25Gbps Retimer Links | 2017年 9月 8日 | ||
| More literature | Advanced Signal Conditioning Made Easy and Efficient | 2017年 1月 12日 | ||
| Analog Design Journal | Green box testing: A method for optimizing high-speed serial links | 2016年 7月 21日 | ||
| Technical article | Designing a 25G system: 5 tips to balance power, performance and price | PDF | HTML | 2016年 2月 1日 | |
| Application note | Understanding EEPROM Programming for 25G and 28G Repeaters and Retimers | 2016年 1月 13日 |
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DS250DF810EVM — 25 Gbps 多速率 8 通道重定時器評估模組
The DS250DF810EVM allows for easy evaluation of the 25 Gbps retimer DS250DF810. Users are required to supply power and high speed traffic to the EVM via Huber+Suhner 1x8 MXP connectors. Huber+Suhner cables are not included.
Through the onboard USB2ANY connection and EVM software, users can evaluate (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ABV) | 135 | Ultra Librarian |
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- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
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