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DS90C3202

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3.3V 8 MHz 至 135 MHz 雙 FPD-Link 接收器

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DS90C3202

最後一次購買
產品規格表 立即訂購

產品詳細資料

Function Deserializer Color depth (bpp) 30 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) Rating Catalog Operating temperature range (°C) 0 to 70
Function Deserializer Color depth (bpp) 30 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) Rating Catalog Operating temperature range (°C) 0 to 70
TQFP (PDT) 128 256 mm² 16 x 16
  • Up to 9.45 Gbit/s data throughput
  • 8 MHz to 135 MHz input clock support
  • Supports up to QXGA panel resolutions
  • Supports HDTV panel resolutions and frame rates up to 1920 x 1080p
  • LVDS 30-bit, 24-bit or 18-bit color data inputs
  • Supports single pixel and dual pixel interfaces
  • Supports spread spectrum clocking
  • Two-wire serial communication interface
  • Programmable clock edge and control strobe select
  • Power down mode
  • +3.3V supply voltage
  • 128-pin TQFP Package
  • Compliant to TIA/EIA-644-A-2001 LVDS Standard

All trademarks are the property of their respective owners.

  • Up to 9.45 Gbit/s data throughput
  • 8 MHz to 135 MHz input clock support
  • Supports up to QXGA panel resolutions
  • Supports HDTV panel resolutions and frame rates up to 1920 x 1080p
  • LVDS 30-bit, 24-bit or 18-bit color data inputs
  • Supports single pixel and dual pixel interfaces
  • Supports spread spectrum clocking
  • Two-wire serial communication interface
  • Programmable clock edge and control strobe select
  • Power down mode
  • +3.3V supply voltage
  • 128-pin TQFP Package
  • Compliant to TIA/EIA-644-A-2001 LVDS Standard

All trademarks are the property of their respective owners.

The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device using the low-power, low-EMI LVDS (Low Voltage Differential Signaling) interface. The DS90C3202 converts up to ten LVDS data streams back into 70 bits of parallel LVCMOS/LVTTL data. The receiver can be programmed with rising edge or falling edge clock. Optional wo-wire serial programming allows fine tuning in development and production environments. With an input clock at 135 MHz, the maximum transmission rate of each LVDS line is 945 Mbps, for an aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This allows the dual 10-bit LVDS Receiver to support resolutions up to HDTV.

The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device using the low-power, low-EMI LVDS (Low Voltage Differential Signaling) interface. The DS90C3202 converts up to ten LVDS data streams back into 70 bits of parallel LVCMOS/LVTTL data. The receiver can be programmed with rising edge or falling edge clock. Optional wo-wire serial programming allows fine tuning in development and production environments. With an input clock at 135 MHz, the maximum transmission rate of each LVDS line is 945 Mbps, for an aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This allows the dual 10-bit LVDS Receiver to support resolutions up to HDTV.
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類型 標題 日期
* Data sheet DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver datasheet (Rev. D) 2013年 4月 12日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點