DS90CF363B
- No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered.
- Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
- "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High.
- 18 to 68 MHz Shift Clock Support
- Best–in–Class Set & Hold Times on TxINPUTs
- Tx Power Consumption < 130 mW (typ) @65MHz Grayscale
- 40% Less Power Dissipation than BiCMOS Alternatives
- Tx Power-Down Mode < 37μW (typ)
- Supports VGA, SVGA, XGA and Dual Pixel SXGA.
- Narrow Bus Reduces Cable Size and Cost
- Up to 1.3 Gbps Throughput
- Up to 170 Megabytes/sec Bandwidth
- 345 mV (typ) Swing LVDS Devices for Low EMI
- PLL Requires no External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 48-lead TSSOP Package
- Improved Replacement for:
- SN75LVDS84, DS90CF363A
All trademarks are the property of their respective owners.
The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90CF363B 3.3V Prog LVDS Transm 18-Bit FPDLink -65 MHz datasheet (Rev. D) | 2013年 4月 17日 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| Application note | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018年 6月 29日 | ||
| Application note | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017年 8月 8日 | ||
| Application note | Receiver Skew Margin for Channel Link I and FPD Link I Devices | 2016年 1月 13日 | ||
| Application note | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004年 5月 15日 | ||
| Application note | AN-1056 STN Application Using FPD-Link | 2004年 5月 14日 | ||
| Application note | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004年 5月 14日 |
設計與開發
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The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
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建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。