LP2951

現行

具電源良好與啟用功能的 100-mA、30-V、低壓降電壓穩壓器

產品詳細資料

Output options Adjustable Output, Fixed Output Iout (max) (A) 0.1 Vin (max) (V) 30 Vin (min) (V) 2 Vout (max) (V) 29 Vout (min) (V) 1.2 Fixed output options (V) 3, 3.3, 5 Rating Catalog Noise (µVrms) 160 PSRR at 100 KHz (dB) 57 Iq (typ) (mA) 0.075 Thermal resistance θJA (°C/W) 52, 97 Load capacitance (min) (µF) 1 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 3 Dropout voltage (Vdo) (typ) (mV) 380 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 0.1 Vin (max) (V) 30 Vin (min) (V) 2 Vout (max) (V) 29 Vout (min) (V) 1.2 Fixed output options (V) 3, 3.3, 5 Rating Catalog Noise (µVrms) 160 PSRR at 100 KHz (dB) 57 Iq (typ) (mA) 0.075 Thermal resistance θJA (°C/W) 52, 97 Load capacitance (min) (µF) 1 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 3 Dropout voltage (Vdo) (typ) (mV) 380 Operating temperature range (°C) -40 to 125
SOIC (D) 8 29.4 mm² 4.9 x 6 WSON (DRG) 8 9 mm² 3 x 3
  • Wide input voltage range
    • VIN range (new chip): 2V to 30V
  • Wide output voltage range VOUT
    • Fixed option: 5.0V, 3.3V, 3V (Legacy Chip)
    • Adjustable option: 1.2V to 29V
  • VOUT accuracy:
    • ±2% over temperature for legacy chip
    • ±0.7% over temperature for new chip
    • ±1% over line, load, and temperature for new chip
  • Output current: Up to 100mA
  • Low IQ (New Chip): 50µA (Typical)
  • Low dropout: 340mV (Typical) at 100mA for new chip
  • Output current limiting and thermal shutdown
  • Open-Drain Error output
  • Stable over a wide range of ceramic output capacitor values
    • COUT range: 1µF to 100µF (New Chip)
    • ESR range: 0 to 2Ω (New Chip)
  • Operating junction temperature: –40°C to 125°C
  • Package option:
    • LP (3-pin TO-92)
    • D (8-pin SOIC)
    • DRG (8-pin WSON)
  • Wide input voltage range
    • VIN range (new chip): 2V to 30V
  • Wide output voltage range VOUT
    • Fixed option: 5.0V, 3.3V, 3V (Legacy Chip)
    • Adjustable option: 1.2V to 29V
  • VOUT accuracy:
    • ±2% over temperature for legacy chip
    • ±0.7% over temperature for new chip
    • ±1% over line, load, and temperature for new chip
  • Output current: Up to 100mA
  • Low IQ (New Chip): 50µA (Typical)
  • Low dropout: 340mV (Typical) at 100mA for new chip
  • Output current limiting and thermal shutdown
  • Open-Drain Error output
  • Stable over a wide range of ceramic output capacitor values
    • COUT range: 1µF to 100µF (New Chip)
    • ESR range: 0 to 2Ω (New Chip)
  • Operating junction temperature: –40°C to 125°C
  • Package option:
    • LP (3-pin TO-92)
    • D (8-pin SOIC)
    • DRG (8-pin WSON)

The LP2951 is a wide input low-dropout regulator (LDO) supporting an input voltage range from 2V to 30V and up to 100mA of load current. LP2951 is able to output either a fixed or adjustable output from the same device. By tying the OUTPUT and SENSE pins together, and the FEEDBACK and VTAP pins together, the LP2950/LP2951 can give 5V or 3.3V fixed output voltages. Alternatively, by leaving the SENSE and VTAP pins open and connecting FEEDBACK to an external resistor divider, the output can be set to any value between 1.2V to 29V.

The LP2951 has a ERROR output that monitors the voltage at the feedback pin to indicate the status of the output voltage. The SHUTDOWN input and ERROR output can be used for sequencing multiple power supplies in the system.

The LP2951 is available in a 3-pin 4.83mm x 4.83mm TO-92(LP), an 8-pin 4.9mm x 6.0mm SOIC(D), and 8-pin 3mm x 3mm SON(DRG) package.

The LP2951 is a wide input low-dropout regulator (LDO) supporting an input voltage range from 2V to 30V and up to 100mA of load current. LP2951 is able to output either a fixed or adjustable output from the same device. By tying the OUTPUT and SENSE pins together, and the FEEDBACK and VTAP pins together, the LP2950/LP2951 can give 5V or 3.3V fixed output voltages. Alternatively, by leaving the SENSE and VTAP pins open and connecting FEEDBACK to an external resistor divider, the output can be set to any value between 1.2V to 29V.

The LP2951 has a ERROR output that monitors the voltage at the feedback pin to indicate the status of the output voltage. The SHUTDOWN input and ERROR output can be used for sequencing multiple power supplies in the system.

The LP2951 is available in a 3-pin 4.83mm x 4.83mm TO-92(LP), an 8-pin 4.9mm x 6.0mm SOIC(D), and 8-pin 3mm x 3mm SON(DRG) package.

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技術文件

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類型 標題 日期
* Data sheet LP295x Adjustable Micropower Voltage Regulators With Shutdown datasheet (Rev. J) PDF | HTML 2024年 8月 5日
Application note L1 and L2 EV Charger Electric Vehicle Service Equipment Design Considerations (Rev. B) 2021年 6月 9日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note ESR, Stability, and the LDO Regulator (Rev. A) 2020年 1月 7日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Application note Fundamental Theory of PMOS LDO Voltage Regulators (Rev. A) 2018年 8月 17日
EVM User's guide LP2951 EVM User's Guide (Rev. A) 2018年 1月 5日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
Technical article How to use an LDO as a load switch PDF | HTML 2016年 2月 1日
Technical article Two ways LDOs save power in the IoT PDF | HTML 2015年 8月 17日
Technical article How to use an LDO to protect a power source PDF | HTML 2015年 7月 25日
Application note A Topical Index of TI Supply Voltage Supervisor (SVS) Application Notes 2015年 6月 15日
Analog Design Journal Techniques for accurate PSRR measurements 2013年 10月 28日
Application note AN-1028 Maximum Power Enhancement Techniques for Power Packages (Rev. B) 2013年 5月 6日
Application note AN-1482 LDO Regulator Stability Using Ceramic Output Capacitors (Rev. A) 2013年 4月 25日
Application note AN-1815 LDOs Ease the Stress of Start-Up (Rev. A) 2013年 4月 24日
Application note AN-1061 Power Conversion in Line-Powered Equipment (Rev. B) 2013年 4月 23日
Application note AN-1950 Silently Powering Low Noise Applications (Rev. A) 2013年 4月 22日
Application note LDO Performance Near Dropout 2010年 10月 8日
Application note 3.6V – 5.5V Input, LDO Reference Design for MSP430 (Rev. A) 2010年 6月 14日
Application note 3.6V – 5.5V Input, LDO with Dual-Level Output Reference Design for MSP430 (Rev. A) 2010年 6月 14日
Application note Packaging Limits Range of Linear Regulators 2010年 5月 8日
Application note Simple Power Solution Using LDOs for the DM365 (Rev. A) 2009年 9月 11日
Application note Digital Designer's Guide to Linear Voltage Regulators & Thermal Mgmt (LDO) (Rev. A) 2008年 6月 4日
Application note Low-Voltage Current Loop Transmitter 2007年 8月 2日
Application note Battery Charging 2007年 3月 21日
Application note Linear and Switching Voltage Regulator Fundamental Part 1 2007年 3月 21日
Application note Ceramic Capacitors Replace Tantalum Capacitors in LDOs (Rev. A) 2006年 10月 13日
Application note Understanding LDO Dropout 2005年 5月 9日
White paper Versatility of the LM5030 PWM Push-Pull Controller 2003年 12月 1日
Application note Extending the Input Voltage Range of an LDO Regulator 2002年 8月 16日
Application note Understanding the Terms and Definitions of LDO Voltage Regulators 1999年 10月 21日
Application note Technical Review of Low Dropout Voltage Regulator Operation And Performance 1999年 8月 30日
Application brief Low Power 150-mA LDO Linear Regulators. Extended Output Voltage Adjustment Range 1999年 6月 11日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

LP2951EVM — LP2951 固定/可調整微功耗低壓差 (LDO) 穩壓器評估模組

The LP2951 devices are bipolar low-dropout (LDO) voltage regulators that can accommodate a wide input supply-voltage range of up to 30 V with an output load up to 100 mA. The LP2951EVM allows for flexibility in design, allowing the user to add or remove input and output capacitors, as well as (...)
使用指南: PDF
TI.com 無法提供
模擬型號

LP2951 PSpice Transient Model (Rev. A)

SNVM037A.ZIP (23 KB) - PSpice Model
模擬型號

LP2951 Unencrypted PSpice Transient Model

SNVMAO3.ZIP (1 KB) - PSpice Model
參考設計

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This reference design realizes a reinforced isolated three-phase inverter subsystem using isolated IGBT gate drivers and isolated current/voltage sensors. The UCC23513 gate driver used has a 6-pin wide body package with optical LED emulated inputs which enables its use as pin-to-pin replacement to (...)
Design guide: PDF
電路圖: PDF
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這是一款精巧的 30-V DC、400-W 參考設計,適合介於 400 Hz 和 800 Hz 之間的主電源頻率的航空電子應用。採用 UCC28064A 為基礎的雙相交錯轉換模式 (TM) 功率因數校正 (PFC),可修正功率因數,並將輸入電流的諧波含量降到最低。DC/DC 使用具有 UCC256404 的 HB-LLC 階段進行實作。在二次側使用同步整流可進一步提升效率。
Test report: PDF
參考設計

TIDA-010076 — 菊輪鍊電力和數據透過單對乙太網路 (T1) 輸送的參考設計

The TIDA-010076 shows the transfer of 220-W power and 100-Mbit/s data over SPE. Communication systems in daisy-chain topology need significantly less hardware and wiring than conventional systems in star-topology. When combined with single-pair Ethernet (SPE, 100BASE-T1) and power over data line, (...)
Design guide: PDF
電路圖: PDF
參考設計

PMP21872 — 外型精巧 12-Vin、1-Vout 40-A 雙相同步降壓參考設計

This reference design is a dual-phase synchronous buck solution using TPS53622 controller with two CSD95490Q5MC power-stage ICs. It takes a 12-V input and converts it to 1-V out at 40 A; 20 A per phase.
Test report: PDF
電路圖: PDF
參考設計

PMP20852 — 3W 隔離三路輸出返馳式轉換器參考設計

PMP20852 is an isolated flyback converter reference design with primary-side regulation using the UCC2805 controller IC. There are three independently isolated outputs on the secondary side, each of which use LP2951 linear regulators to provide a well-regulated 16V output on each of the three (...)
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
WSON (DRG) 8 Ultra Librarian

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