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THS4531A

現行

超低功耗、RRO、全差動放大器

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產品規格表

THS4531A

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 BW at Acl (MHz) 36 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 0.25 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.4 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 26 2nd harmonic (dBc) 129 3rd harmonic (dBc) 138 Frequency of harmonic distortion measurement (MHz) 0.001 GBW (typ) (MHz) 27 Input bias current (max) (pA) 250000 Features Shutdown CMRR (typ) (dB) 116 Rating Catalog
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 BW at Acl (MHz) 36 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 0.25 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.4 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 26 2nd harmonic (dBc) 129 3rd harmonic (dBc) 138 Frequency of harmonic distortion measurement (MHz) 0.001 GBW (typ) (MHz) 27 Input bias current (max) (pA) 250000 Features Shutdown CMRR (typ) (dB) 116 Rating Catalog
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9 WQFN (RUN) 10 4 mm² 2 x 2
  • Ultra Low-Power:
    • Voltage: 2.5 V to 5.5 V
    • Current: 250 µA
    • Power-Down Mode: 0.5 µA (Typical)
  • Fully Differential Architecture
  • Bandwidth: 36 MHz (Av = 1 V/V)
  • Slew Rate: 200 V/µs
  • THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
  • High DC Accuracy:
    • VOS: ±100 µV
    • VOS Drift: ±3 µV/˚C (–40°C to +125°C)
    • AOL: 114 dB
  • Rail-to-Rail Output (RRO)
  • Negative Rail Input (NRI)
  • Output Common-Mode Control
  • 8-Pin SOIC (D) and VSSOP (DGK)
  • 10-Pin WQFN (RUN)
  • Ultra Low-Power:
    • Voltage: 2.5 V to 5.5 V
    • Current: 250 µA
    • Power-Down Mode: 0.5 µA (Typical)
  • Fully Differential Architecture
  • Bandwidth: 36 MHz (Av = 1 V/V)
  • Slew Rate: 200 V/µs
  • THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
  • High DC Accuracy:
    • VOS: ±100 µV
    • VOS Drift: ±3 µV/˚C (–40°C to +125°C)
    • AOL: 114 dB
  • Rail-to-Rail Output (RRO)
  • Negative Rail Input (NRI)
  • Output Common-Mode Control
  • 8-Pin SOIC (D) and VSSOP (DGK)
  • 10-Pin WQFN (RUN)

The THS4531A device is a low-power, fully differential amplifier with input common-mode range below the negative rail and rail-to-rail output. The device is designed for low-power data acquisition systems and high-density applications where power consumption and dissipation is critical.

The device features accurate output common-mode control that allows for DC coupling when driving analog-to-digital converters (ADCs). This control, coupled with the input common-mode range below the negative rail and rail-to-rail output, allows for easy interface from single-ended ground-referenced signal sources to successive-approximation registers (SARs), and delta-sigma (ΔΣ) ADCs using only single-supply 2.5-V to 5-V power. The THS4531A is also a valuable tool for general-purpose, low-power differential signal conditioning applications.

The THS4531A device is a low-power, fully differential amplifier with input common-mode range below the negative rail and rail-to-rail output. The device is designed for low-power data acquisition systems and high-density applications where power consumption and dissipation is critical.

The device features accurate output common-mode control that allows for DC coupling when driving analog-to-digital converters (ADCs). This control, coupled with the input common-mode range below the negative rail and rail-to-rail output, allows for easy interface from single-ended ground-referenced signal sources to successive-approximation registers (SARs), and delta-sigma (ΔΣ) ADCs using only single-supply 2.5-V to 5-V power. The THS4531A is also a valuable tool for general-purpose, low-power differential signal conditioning applications.
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類型 標題 日期
* Data sheet THS4531A Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier datasheet (Rev. D) PDF | HTML 2020年 3月 4日
Product overview Pairing ADC Drivers With Fully-Differential Input ADCs for Wide Bandwidth Data Acquisition 2024年 4月 1日
Application brief Maximizing System Total Harmonic Distortion Using High Speed Amplifiers 2018年 6月 20日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
Application note Fully-Differential Amplifiers (Rev. E) 2016年 9月 19日
EVM User's guide THS4531ADGKEVM Evaluation Module 2012年 12月 5日
Analog Design Journal Using fully differential op amps as attenuators, Part 3 2009年 10月 4日
Analog Design Journal Using fully differential op amps as attenuators, Part 2 2009年 7月 14日
Analog Design Journal Using fully differential op amps as attenuators, Part 1 2009年 5月 1日
Analog Design Journal Analysis of fully differential amplifiers 2005年 3月 11日
Analog Design Journal Designing for low distortion with high-speed op amps 2005年 3月 2日
Application note Noise Analysis for High Speed Op Amps (Rev. A) 2005年 1月 17日

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開發板

THS4531ADGKEVM — THS4531ADGKEVM 評估模組

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模擬型號

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SLOM262.TSC (3751 KB) - TINA-TI Reference Design
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SLOM352A.TSC (68 KB) - TINA-TI Reference Design
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THS4531A TINA-TI Spice Model (Rev. A)

SLOM351A.ZIP (15 KB) - TINA-TI Spice Model
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SLOR110.ZIP (315 KB)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
WQFN (RUN) 10 Ultra Librarian
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