驅動程式或資料庫
TLC696XX-DESIGN — TLC696XX design resources
TLC696XX design resources
TLC69699-Q1
- AEC-Q100 qualified for automotive applications
- Grade 1: –40°C to 125°C ambient temperature
- Device HBM classification level H3A
- Device CDM classification level C5
- Functional Safety-Capable:
- Documentation available to aid functional safety system design
- Operating voltage VCC range: 2.5V to 5.5V
- SPI peripheral
- Data transfer rate up to 20MHz
- Support multiple peripherals with one controller
- Continuous Clock Serial Interface (CCSI) Controller and Peripheral
- Data transfer rate up to 20MHz
- Programmable clock jitter for EMI enhancement
- Diagnostics
- Open-drain FAULT pin
- SPI communication loss detection
- CRC for SPI communication
- Continuous clock watchdog
- CCSI data integrity
- Data ready interrupt for availability of data
The TLC69699-Q1 SPI-compatible connectivity enables TLC696xx-Q1 device family to be controlled using a standard SPI controller. The device features an internal oscillator to generate the continuous clock required by the TLC696xx-Q1 device family. Jitter can be added to the continuous clock for EMI enhancement. The transmitted data is aligned to the continuous clock to maintain the timing requirements of the CCSI interface.
TLC69699-Q1 incorporates reporting of faults in both the TLC696xx-Q1 daisy chain and TLC69699-Q1 internal. Data transmission of register and brightness to the TLC696xx-Q1 daisy chain is CRC protected by TLC69699-Q1. In addition, both the data and continuous clock lines are guarded by TLC69699-Q1 for stuck-at faults.
技術文件
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檢視所有 1 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | TLC69699-Q1 Automotive SPI-Compatible Connectivity for TLC696xx-Q1 Device Family datasheet | PDF | HTML | 2024年 9月 23日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
TLC69699DYYEVM — TLC69699 評估模組
TLC69699 是 TLC696xx 系列 CCSI 和 SPI 間的連線 IC。TLC69699DYYEVM 用於評估連線 IC TLC69699 的特性、運作及使用狀況。TLC69699DYYEVM 旨在與 TLC69661EVM 和 TLC69668EVM 配合使用。
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23-THN (DYY) | 14 | Ultra Librarian |
| WSON (DRR) | 12 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。