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監控器和重設 IC

TPS3828-Q1

現行

具看門狗定時器的車用電壓監控器

立即訂購
產品規格表

TPS3828-Q1

現行
產品規格表 立即訂購

產品詳細資料

Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 2.93, 4.55 Features Manual reset capable, Undervoltage monitor only, Watchdog timer Reset threshold accuracy (%) 2.4 Iq (typ) (mA) 0.015 Output driver type/reset output Active-low, Open-drain Time delay (ms) 200 Supply voltage (min) (V) 1.1 Supply voltage (max) (V) 5.5 Rating Automotive Watchdog timer WDI (s) 1.6 Operating temperature range (°C) -40 to 125
Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 2.93, 4.55 Features Manual reset capable, Undervoltage monitor only, Watchdog timer Reset threshold accuracy (%) 2.4 Iq (typ) (mA) 0.015 Output driver type/reset output Active-low, Open-drain Time delay (ms) 200 Supply voltage (min) (V) 1.1 Supply voltage (max) (V) 5.5 Rating Automotive Watchdog timer WDI (s) 1.6 Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8
  • Qualified for automotive applications
  • AEC-Q100 Qualified With the Following Results:
    • Device temperature grade 1: –40°C to 125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • ESD protection exceeds 2000 V Per MIL-STD-883, Method 3015; using human body model (C = 100 pF, R = 1500 Ω)
  • Power-on reset generator with fixed delay time of 200 ms (TPS3823/4/5/8-xx-Q1) or 25 ms (TPS3820-xx-Q1)
  • Manual reset input (TPS3820/3/5/8-xx-Q1)
  • Reset output available in active-low (TPS3820/3/4/5-xx-Q1), Active-High (TPS3824/5-xx-Q1), and open drain (TPS3828-xx-Q1)
  • Supply voltage supervision range:
    2.5 V, 3 V, 3.3 V, 5 V
  • Watchdog timer (TPS3820/3/4/8-xx-Q1)
  • Supply current of 15 µA (Typical)
  • 5-Pin SOT-23 package
  • Temperature range: −40°C to 125°C
  • Qualified for automotive applications
  • AEC-Q100 Qualified With the Following Results:
    • Device temperature grade 1: –40°C to 125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B
  • ESD protection exceeds 2000 V Per MIL-STD-883, Method 3015; using human body model (C = 100 pF, R = 1500 Ω)
  • Power-on reset generator with fixed delay time of 200 ms (TPS3823/4/5/8-xx-Q1) or 25 ms (TPS3820-xx-Q1)
  • Manual reset input (TPS3820/3/5/8-xx-Q1)
  • Reset output available in active-low (TPS3820/3/4/5-xx-Q1), Active-High (TPS3824/5-xx-Q1), and open drain (TPS3828-xx-Q1)
  • Supply voltage supervision range:
    2.5 V, 3 V, 3.3 V, 5 V
  • Watchdog timer (TPS3820/3/4/8-xx-Q1)
  • Supply current of 15 µA (Typical)
  • 5-Pin SOT-23 package
  • Temperature range: −40°C to 125°C

For all new designs with TPS3820-xx-Q1, use the TPS3820-xxQPDBVRQ1 part number. The TPS3820-xxQP is functionally equivalent and a replacement to the TPS3820xxQ. The TPS3820-xxQDBVRQ1 is not recommended for new designs (NRND).

The TPS382x-xx-Q1 family of supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET asserts when the supply voltage VDD becomes greater than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active low as long as VDD remains below the threshold voltage, VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage VIT−. When the supply voltage drops below the threshold voltage VIT−, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal voltage divider. The TPS382x-xx-Q1 family also offers watchdog time out options of 200 ms (TPS3820-xx-Q1) and 1.6 s (TPS3823/4/8-xx-Q1).

For all new designs with TPS3820-xx-Q1, use the TPS3820-xxQPDBVRQ1 part number. The TPS3820-xxQP is functionally equivalent and a replacement to the TPS3820xxQ. The TPS3820-xxQDBVRQ1 is not recommended for new designs (NRND).

The TPS382x-xx-Q1 family of supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET asserts when the supply voltage VDD becomes greater than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active low as long as VDD remains below the threshold voltage, VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage VIT−. When the supply voltage drops below the threshold voltage VIT−, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal voltage divider. The TPS382x-xx-Q1 family also offers watchdog time out options of 200 ms (TPS3820-xx-Q1) and 1.6 s (TPS3823/4/8-xx-Q1).
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類型 標題 日期
* Data sheet TPS382x-xx-Q1 Voltage Monitor With Watchdog Timer datasheet (Rev. D) PDF | HTML 2019年 7月 17日
Functional safety information TPS382x-Q1 Functional Safety FIT Rate and Failure Mode Distribution 2019年 12月 19日
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics 2019年 6月 28日
Design guide TIDA-00143 Overview 2014年 4月 28日
User guide TIDA-00143 Quick Start Guide 2014年 4月 28日
Test report TIDA-00143 Test Results 2014年 4月 28日

設計與開發

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開發板

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The TPS382-Q1EVM evaluation module (EVM) has five different TPS382x-Q1 devices to let you evaluate and test the different features of the product family.  The EVM includes devices with 2.5-V, 3-V, 3.3-V and 5-V fixed monitoring, watchdog input, manual reset, (...)
使用指南: PDF
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TIDA-00143 BOM

TIDR557.PDF (108 KB)
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Gerber 檔案

TIDA-00143 Gerber

TIDC389.ZIP (826 KB)
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配置圖

TIDA-00143 Design File

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配置圖

TIDA-00143 Schematic and Block Diagram

TIDR556.PDF (711 KB)
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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參考設計

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Design guide: PDF
電路圖: PDF
參考設計

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此參考設計展示了頻寬最佳化類比前端 (AFE) 和即時 FIR 實作，使用低功率擷取任何波形中的寬頻頻譜。各訊號路徑中的運算放大器，是根據增益、訊號頻寬、低雜訊，以及在消耗低功率的同時接近軌擺幅需求來選擇。波形可在頻率和時域中，使用含內建向量數學引擎的混合訊號超低功率微處理器進行即時處理。
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電路圖: PDF
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