TPS54325

現行

4.5V 至 18V 輸入、3A 同步降壓轉換器

產品詳細資料

Rating Catalog Operating temperature range (°C) -40 to 85 Topology Buck Type Converter Iout (max) (A) 3 Vin (min) (V) 4.5 Vin (max) (V) 18 Switching frequency (min) (kHz) 700 Switching frequency (max) (kHz) 700 Features Enable, Power good, Soft Start Adjustable, Synchronous Rectification Control mode D-CAP2 Vout (min) (V) 0.76 Vout (max) (V) 5.5 Iq (typ) (µA) 850 Duty cycle (max) (%) 90
Rating Catalog Operating temperature range (°C) -40 to 85 Topology Buck Type Converter Iout (max) (A) 3 Vin (min) (V) 4.5 Vin (max) (V) 18 Switching frequency (min) (kHz) 700 Switching frequency (max) (kHz) 700 Features Enable, Power good, Soft Start Adjustable, Synchronous Rectification Control mode D-CAP2 Vout (min) (V) 0.76 Vout (max) (V) 5.5 Iq (typ) (µA) 850 Duty cycle (max) (%) 90
HTSSOP (PWP) 14 32 mm² 5 x 6.4
  • D-CAP2™ Mode Enables Fast Transient Response
  • Low Output Ripple and Allows Ceramic Output Capacitor
  • Wide VCC Input Voltage Range: 4.5 V to 18 V
  • Wide VIN Input Voltage Range: 2.0 V to 18 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Highly Efficient Integrated FET’s Optimized for
    Lower Duty Cycle Applications – 120 mΩ (High Side)
    and 70 mΩ (Low Side)
  • High Efficiency, less than 10 µA at shutdown
  • High Initial Bandgap Reference Accuracy
  • Adjustable Soft Start
  • Pre-Biased Soft Start
  • 700-kHz Switching Frequency (fSW)
  • Cycle By Cycle Over Current Limit
  • Power Good Output
  • D-CAP2™ Mode Enables Fast Transient Response
  • Low Output Ripple and Allows Ceramic Output Capacitor
  • Wide VCC Input Voltage Range: 4.5 V to 18 V
  • Wide VIN Input Voltage Range: 2.0 V to 18 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Highly Efficient Integrated FET’s Optimized for
    Lower Duty Cycle Applications – 120 mΩ (High Side)
    and 70 mΩ (Low Side)
  • High Efficiency, less than 10 µA at shutdown
  • High Initial Bandgap Reference Accuracy
  • Adjustable Soft Start
  • Pre-Biased Soft Start
  • 700-kHz Switching Frequency (fSW)
  • Cycle By Cycle Over Current Limit
  • Power Good Output

The TPS54325 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325 device enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.

The main control loop for the TPS54325 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C.

The TPS54325 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325 device enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.

The main control loop for the TPS54325 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C.

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類型 標題 日期
* Data sheet TPS54325 4.5-V to 18-V, 3-A Output Synchronous Step Down Switcher with Integrated FET datasheet (Rev. F) PDF | HTML 2014年 11月 23日
Analog Design Journal Control-Mode Quick Reference Guide (Rev. B) PDF | HTML 2023年 8月 29日
User guide TPS54325 Step-Down Converter Evaluation Module User's Guide (Rev. A) PDF | HTML 2021年 10月 11日
Application note D-CAP2 Frequency Response Model, based on frequency domain analysis of Fixed On- 2013年 1月 2日
Application note Understanding Thermal Dissipation and Design of a Heatsink 2011年 5月 4日
Analog Design Journal Efficiency of synchronous versus nonsynchronous buck converters 2009年 10月 4日

設計與開發

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開發板

TPS54325EVM — 5V 至 17V 輸入、3A 轉換器評估模組

The TPS54325EVM (evaluation module) is a fully assembled and tested circuit for evaluating the TPS54428 synchronous step-down converter. The EVM operates from a 4.5-V to 18-V input and provides a 1.05-V output up to 3-A load. The main control loop of TPS54325 uses D-CAP2™ mode control, which (...)

使用指南: PDF | HTML
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模擬型號

TPS54325 TINA-TI Reference Design

SLVM201.TSC (168 KB) - TINA-TI Reference Design
模擬型號

TPS54325 TINA-TI Transient Spice Model

SLVM200.ZIP (40 KB) - TINA-TI Spice Model
模擬型號

TPS54325 Unencrypted PSpice Transient Model Package (Rev. A)

SLIM285A.ZIP (41 KB) - PSpice Model
參考設計

TIDA-010011 — 用於保護繼電器處理器模組的高效電源供應架構參考設計

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
電路圖: PDF
參考設計

PMP5411 — 通用 AC 40W 機上盒電源供應 (1.2V @ 3A)

This reference evaluation module is an example of complete power-trees inside a set-top-box.
It performs an AC-DC conversion, then, DC-DC conversions for 1.2V/1.8V/2.5V/3.3V/5V rails.
Test report: PDF
電路圖: PDF
參考設計

PMP8251 — 適用於 Xilinx FPGA Zynq 7 的電源解決方案 (1.8V@0.15A)

This reference design features multiple TPS54325 and other power devices for Xilinx Zynq FPGA. From 12-V input, this reference design has the power rails required by Zynq FPGA, including DDR3 memory.
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HTSSOP (PWP) 14 Ultra Librarian

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