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線性與低壓差 (LDO) 穩壓器

TPS74401

現行

3-A、低 VIN (0.8-V)、低雜訊、高 PSRR、可調式超低壓降電壓穩壓器

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TPS74401

現行
產品規格表 立即訂購

產品詳細資料

Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 13 PSRR at 100 KHz (dB) 50 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 115 Operating temperature range (°C) -40 to 125
Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Rating Catalog Noise (µVrms) 13 PSRR at 100 KHz (dB) 50 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 27 Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 115 Operating temperature range (°C) -40 to 125
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGR) 20 12.25 mm² 3.5 x 3.5 VQFN (RGW) 20 25 mm² 5 x 5
  • Input voltage range: 1.1V to 5.5V
  • Adjustable start-up in-rush control
  • 1% accuracy over line, load, and temperature

  • VBIAS permits low VIN operation with good transient response

  • Adjustable output: 0.8V to 3.6V
  • Ultra-low dropout:
    • 115mV (typical) (legacy chip) at 3.0A
    • 120mV (typical) (new chip) at 3.0A
  • Stable with any or no output capacitor (legacy chip)

  • Stable with any output capacitor ≥2.2µF (new chip)

  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Packages:
    • 5mm × 5mm × 1mm VQFN (RGW)
    • 3.5mm × 3.5mm VQFN (RGR), and DDPAK-7 (legacy chip only)
  • Input voltage range: 1.1V to 5.5V
  • Adjustable start-up in-rush control
  • 1% accuracy over line, load, and temperature

  • VBIAS permits low VIN operation with good transient response

  • Adjustable output: 0.8V to 3.6V
  • Ultra-low dropout:
    • 115mV (typical) (legacy chip) at 3.0A
    • 120mV (typical) (new chip) at 3.0A
  • Stable with any or no output capacitor (legacy chip)

  • Stable with any output capacitor ≥2.2µF (new chip)

  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Packages:
    • 5mm × 5mm × 1mm VQFN (RGW)
    • 3.5mm × 3.5mm VQFN (RGR), and DDPAK-7 (legacy chip only)

The TPS74401 low-dropout (LDO) linear regulators provide an easy-to-use robust power-management option for a wide variety of applications. The user-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. Complete flexibility lets the user configure a plan that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with specific start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The device is stable without an output capacitor (legacy chip) or with any type of capacitor ≥ 2.2µF (new chip). The device is fully specified from TJ = –40°C to 125°C.

The TPS74401 low-dropout (LDO) linear regulators provide an easy-to-use robust power-management option for a wide variety of applications. The user-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. Complete flexibility lets the user configure a plan that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with specific start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. The device is stable without an output capacitor (legacy chip) or with any type of capacitor ≥ 2.2µF (new chip). The device is fully specified from TJ = –40°C to 125°C.

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類型 標題 日期
* Data sheet TPS74401 3.0A, Ultra-LDO With Programmable Soft-Start datasheet (Rev. S) PDF | HTML 2024年 11月 15日
White paper Demystifying LDO Turn-On (startup) Time PDF | HTML 2024年 10月 5日
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020年 8月 18日
Application note Using Thermal Calculation Tools for Analog Components (Rev. A) 2019年 8月 30日
Application note A Topical Index of TI LDO Application Notes (Rev. F) 2019年 6月 27日
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 2018年 3月 21日
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
Analog Design Journal 4Q 2012 Issue Analog Applications Journal 2012年 9月 25日
Analog Design Journal LDO noise examined in detail 2012年 9月 25日
Application note Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B) 2010年 8月 26日
Application note Power Ref Design for TMS320C6472, 12-Vin Digital Pwr Cntrlrs, and LDOs (Rev. A) 2010年 5月 24日
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010年 4月 28日
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010年 3月 26日
Application note Using New Thermal Metrics 2009年 12月 15日
Analog Design Journal A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W 2006年 10月 10日
EVM User's guide TPS74x01EVM-118 User's Guide 2006年 6月 20日

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模擬型號

TPS74401 PSpice Transient Model (Rev. B)

SLIM008B.ZIP (63 KB) - PSpice Model
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TPS74401 TINA-TI DC Reference Design

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TPS74401 TINA-TI Transient Reference Design

SLIM009.TSC (89 KB) - TINA-TI Reference Design
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TPS74401 TINA-TI Transient Spice Model

SLIM011.ZIP (35 KB) - TINA-TI Spice Model
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TPS74401 Unencrypted PSpice Transient Model

SBVM619.ZIP (3 KB) - PSpice Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TO-263 (KTW) 7 Ultra Librarian
VQFN (RGR) 20 Ultra Librarian
VQFN (RGW) 20 Ultra Librarian
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