UC1708
- 3.0A Peak Current Totem Pole Output
- 5 to 35V Operation
- 25ns Rise and Fall Times
- 25ns Propagation Delays
- Thermal Shutdown and Under-Voltage Protection
- High-Speed, Power MOSFET Compatible
- Efficient High Frequency Operation
- Low Cross-Conduction Current Spike
- Enable and Shutdown Functions
- Wide Input Voltage Range
- ESD Protection to 2kV
The UC1708 family of power drivers is made with a high-speed, high-voltage, Schottky process to interface control functions and high-power switching devices particularly power MOSFETs. Operating over a 5 V to 35 V supply range, these devices contain two independent channels. The A and B inputs are compatible with TTL and CMOS logic families, but can withstand input voltages as high as VIN. Each output can source or sink up to 3 A as long as power dissipation limits are not exceeded.
Although each output can be activated independently with its own inputs, they can be forced low in common through the action of either a digital high signal at the Shutdown terminal or by forcing the Enable terminal low. The Shutdown terminal will only force the outputs low, it will not effect the behavior of the rest of the device. The Enable terminal effectively places the device in under-voltage lockout, reducing power consumption by as much as 90%. During under-voltage and disable (Enable terminal forced low) conditions, the outputs are held in a self-biasing, low-voltage, state.
The UC3708 and UC2708 are available in plastic 8-pin MINI DIP and 16-pin bat-wing DIP packages for commercial operation over a 0°C to 70°C temperature range and industrial temperature range of -25°C to 85°C respectively. For operation over a -55°C to 125°C temperature range, the UC1708 is available in hermetically sealed 8-pin MINI CDIP, 16 pin CDIP and 20 pin CLCC packages. Surface mount devices are also available.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | Dual Non-Inverting Power Driver datasheet (Rev. C) | 2007年 9月 25日 | |
* | SMD | UC1708 SMD 5962-00514 | 2016年 6月 21日 | |
Application note | Review of Different Power Factor Correction (PFC) Topologies' Gate Driver Needs | PDF | HTML | 2024年 1月 22日 | |
Application brief | External Gate Resistor Selection Guide (Rev. A) | 2020年 2月 28日 | ||
Application brief | Understanding Peak IOH and IOL Currents (Rev. A) | 2020年 2月 28日 | ||
Application brief | How to overcome negative voltage transients on low-side gate drivers' inputs | 2019年 1月 18日 | ||
Application note | DN-35 IGBT Drive Using MOSFET Gate Drivers (Rev. A) | 2018年 6月 21日 | ||
Application note | U-118 New Driver ICs Optimize High-Speed Power MOSFET Switching Characteristics | 1999年 9月 5日 | ||
Application note | U-137 Practical Considerations in High Performance MOSFET, IGBT and MCT Gate | 1999年 9月 5日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
CDIP (J) | 16 | Ultra Librarian |
CDIP (JG) | 8 | Ultra Librarian |
LCCC (FK) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點