UCC21220A

現行

適用於 MOSFET 和 GaNFET 且具有停用針腳和 5V UVLO 的 3.0kVrms、4A/6A 雙通道隔離式閘極驅動器

產品詳細資料

Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch IGBT, MOSFET Peak output current (A) 6 Features Disable Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 6 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 5
Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Working isolation voltage (VIOWM) (Vrms) 990 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch IGBT, MOSFET Peak output current (A) 6 Features Disable Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 6 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 990 Rise time (ns) 5 Fall time (ns) 6 Undervoltage lockout (typ) (V) 5
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Supports basic and functional isolation
  • CMTI greater than 100V/ns
  • 4A peak source, 6A peak sink output
  • Switching parameters:
    • 40ns maximum propagation delay
    • 5ns maximum delay matching
    • 5.5ns maximum pulse-width distortion
    • 35µs maximum VDD power-up delay
  • Up to 18V VDD output drive supply
    • 5V and 8V VDD UVLO Options
  • Operating temperature range (TA) –40°C to 125°C
  • Narrow body SOIC-16 (D) package
  • Rejects input pulses shorter than 5ns
  • TTL and CMOS compatible inputs
  • Safety-related certifications:
    • 4242VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1 (planned)
    • 3000VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2011 (planned)
  • Supports basic and functional isolation
  • CMTI greater than 100V/ns
  • 4A peak source, 6A peak sink output
  • Switching parameters:
    • 40ns maximum propagation delay
    • 5ns maximum delay matching
    • 5.5ns maximum pulse-width distortion
    • 35µs maximum VDD power-up delay
  • Up to 18V VDD output drive supply
    • 5V and 8V VDD UVLO Options
  • Operating temperature range (TA) –40°C to 125°C
  • Narrow body SOIC-16 (D) package
  • Rejects input pulses shorter than 5ns
  • TTL and CMOS compatible inputs
  • Safety-related certifications:
    • 4242VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1 (planned)
    • 3000VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2011 (planned)

The UCC21220 and UCC21220A devices are basic and functional isolated dual-channel gate drivers with 4A peak-source and 6A peak-sink current. They are designed to drive power MOSFETs and GaNFETs in PFC, Isolated DC/DC, and synchronous rectification applications, with fast switching performance and robust ground bounce protection through greater than 100V/ns common-mode transient immunity (CMTI).

These devices can be configured as two low-side drivers, two high-side drivers, or half-bridge drivers. Two outputs can be paralleled to form a single driver which doubles the drive strength for heavy load conditions due to the best-in-class delay matching performance.

Protection features include the following: DIS pin shuts down both outputs simultaneously when it is set high, INA/B pin rejects input transient shorter than 5ns, both inputs and outputs can withstand –2V spikes for 200ns, all supplies have undervoltage lockout (UVLO), and active pulldown protection clamps the output below 2.1V when unpowered or floated.

With these features, these devices enable high efficiency, high power density, and robustness in a wide variety of power applications.

The UCC21220 and UCC21220A devices are basic and functional isolated dual-channel gate drivers with 4A peak-source and 6A peak-sink current. They are designed to drive power MOSFETs and GaNFETs in PFC, Isolated DC/DC, and synchronous rectification applications, with fast switching performance and robust ground bounce protection through greater than 100V/ns common-mode transient immunity (CMTI).

These devices can be configured as two low-side drivers, two high-side drivers, or half-bridge drivers. Two outputs can be paralleled to form a single driver which doubles the drive strength for heavy load conditions due to the best-in-class delay matching performance.

Protection features include the following: DIS pin shuts down both outputs simultaneously when it is set high, INA/B pin rejects input transient shorter than 5ns, both inputs and outputs can withstand –2V spikes for 200ns, all supplies have undervoltage lockout (UVLO), and active pulldown protection clamps the output below 2.1V when unpowered or floated.

With these features, these devices enable high efficiency, high power density, and robustness in a wide variety of power applications.

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類型 標題 日期
* Data sheet UCC21220, UCC21220A 4A, 6A, Dual-Channel Basic and Functional Isolated Gate Drivers with High Noise Immunity datasheet (Rev. F) PDF | HTML 2024年 2月 2日
Certificate VDE Certificate for Basic Isolation for DIN EN IEC 60747-17 (Rev. W) 2024年 1月 31日
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design 2020年 4月 24日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日
Certificate UL Certification E181974 Vol 4. Sec 9 (Rev. A) 2019年 7月 22日
User guide Gate Drive Voltage vs. Efficiency 2019年 4月 25日
Application brief How to Drive High Voltage GaN FETs with UCC21220A 2019年 3月 6日
White paper Impact of an isolated gate driver (Rev. A) 2019年 2月 20日
Application note Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers 2018年 7月 19日
White paper Demystifying high-voltage power electronics for solar inverters 2018年 6月 6日
Application note Solar Inverter Layout Considerations for UCC21220 2018年 6月 6日
EVM User's guide UCC21220EVM-009 User's Guide (Rev. B) 2018年 4月 12日

設計與開發

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開發板

UCC21220EVM-009 — UCC21220 4A、6A 3.0kVRMS 隔離式雙通道閘極驅動器評估模組

UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
使用指南: PDF
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模擬型號

UCC21220AD PSpice Transient Model

SLUM649.ZIP (58 KB) - PSpice Model
模擬型號

UCC21220AD Unencrypted PSpice Transient Model

SLUM650.ZIP (3 KB) - PSpice Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計

PMP30446 — 具有標準 Si-MOSFET 的 99% 峰值效率、585-W 高電壓降壓參考設計

This reference design converts a DC-input source in the range of 450 V to 780 V into non-isolated 390 V at 1.5 A. This is an alternative solution to SiC-FET and SiC-Diode buck converter, since the actual power stage uses only standard silicon components. In order to employ 600 V rated devices, the (...)
Test report: PDF
電路圖: PDF
參考設計

PMP40500 — 54-VDC 輸入、12-V 42-A 輸出半橋參考設計

此 12-V、42-A 輸出半橋式參考設計適合有線網路園區與分公司交換器中的匯流排轉換器。此設計具高效率及各種故障保護 (過電流和短路)。設計採用 3 kVRMS 基本及功能隔離式閘極驅動器 UCC21220D、UCC21220AD、UCC21222D,及 5.7-kRMS 強化隔離式閘極驅動器 UCC21540D、UCC21540DWK 及 UCC21541DW 以提供效率比較。
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 16 Ultra Librarian

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