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隔離式閘極驅動器

UCC21541

現行

採用 DW 封裝且具有 8V UVLO、雙輸入、停用針腳的 5.7kVrms、1.5A/2.5A 雙通道絕緣式閘極驅動器

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產品規格表

UCC21541

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5000 Working isolation voltage (VIOWM) (Vrms) 1414 Transient isolation voltage (VIOTM) (VPK) 7070 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 2.5 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 1414 Rise time (ns) 8 Fall time (ns) 9 Undervoltage lockout (typ) (V) 8
Number of channels 2 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5000 Working isolation voltage (VIOWM) (Vrms) 1414 Transient isolation voltage (VIOTM) (VPK) 7070 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 2.5 Features Disable, Programmable dead time Output VCC/VDD (max) (V) 18 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 1414 Rise time (ns) 8 Fall time (ns) 9 Undervoltage lockout (typ) (V) 8
SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • Wide body package options
    • DW SOIC-16: pin-2-pin to UCC21520
    • DWK SOIC-14: 3.3 mm Ch-2-Ch spacing
  • Up to 4-A peak source and 6-A peak sink output
  • Up to 18-V VDD output drive supply
    • 5-V and 8-V VDD UVLO Options
  • CMTI greater than 100 V/ns
  • Switching parameters:
    • 40-ns maximum propagation delay
    • 5-ns maximum delay matching
    • 5.5-ns maximum pulse-width distortion
    • 35-µs maximum VDD power-up delay
  • Resistor-programmable dead time
  • TTL and CMOS compatible inputs
  • Safety-related certifications:
    • 8000-VPK reinforced isolation per DIN V VDE V 0884-11:2017-01
    • 5700-VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2011
  • Wide body package options
    • DW SOIC-16: pin-2-pin to UCC21520
    • DWK SOIC-14: 3.3 mm Ch-2-Ch spacing
  • Up to 4-A peak source and 6-A peak sink output
  • Up to 18-V VDD output drive supply
    • 5-V and 8-V VDD UVLO Options
  • CMTI greater than 100 V/ns
  • Switching parameters:
    • 40-ns maximum propagation delay
    • 5-ns maximum delay matching
    • 5.5-ns maximum pulse-width distortion
    • 35-µs maximum VDD power-up delay
  • Resistor-programmable dead time
  • TTL and CMOS compatible inputs
  • Safety-related certifications:
    • 8000-VPK reinforced isolation per DIN V VDE V 0884-11:2017-01
    • 5700-VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2011

The UCC2154x is an isolated dual channel gate driver family designed with up to 4-A/6-A peak source/sink current to drive power MOSFET, IGBT, and GaN transistors. UCC2154x in DWK package also offers 3.3-mm minimum channel-to-channel spacing which facilitates higher bus voltage.

The UCC2154xfamily can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5.7-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, integrated de-glitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.

The UCC2154x is an isolated dual channel gate driver family designed with up to 4-A/6-A peak source/sink current to drive power MOSFET, IGBT, and GaN transistors. UCC2154x in DWK package also offers 3.3-mm minimum channel-to-channel spacing which facilitates higher bus voltage.

The UCC2154xfamily can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5.7-kVRMS isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, integrated de-glitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.
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UCC21542 現行 具有 8V UVLO 和 3.3mm 通道間距選項的 5.7kVRMS、4A/6A 雙通道絕緣式閘極驅動器 Non-Programmable deadtime version

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類型 標題 日期
* Data sheet UCC2154x Reinforced Isolation Dual-Channel Gate Driver With 3.3-mm Channel-to-Channel Spacing Option datasheet (Rev. D) PDF | HTML 2021年 1月 4日
Certificate UCC21540 CQC Certificate of Product Certification 2023年 8月 17日
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 2021年 12月 16日
Certificate CQC19001226951 2021年 2月 5日
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design 2020年 4月 24日
EVM User's guide Using the UCC21540EVM 2018年 7月 27日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

UCC21540EVM — 具有 3.3mm 通道至通道間距的 5.0-kVrms 絕緣式雙通道閘極驅動器

UCC21540EVM is designed for evaluating UCC21540, which is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current capability. This EVM serves as a reference design for driving power MOSFETs with up to 18V drive voltage, UCC21540 pin function identification, components (...)
使用指南: PDF
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模擬型號

UCC21541 PSpice Transient Model

SLUM657.ZIP (20 KB) - PSpice Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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參考設計

TIDA-010210 — 以 GaN 為基礎的 11-kW、雙向、三相 ANPC 參考設計

此參考設計提供實作三階三相氮化鎵 (GaN) 型 ANPC 逆變器功率級的設計範本。使用快速切換功率裝置可在更高的 100 kHz 頻率進行切換、減少濾波器的磁性元件尺寸，以及提升功率級的功率密度。多階拓撲允許在高達 1000 V 的較高 DC 匯流排電壓下使用 600-V 額定電源裝置。低切換電壓應力減少切換損耗，導致峰值效率達 98.5%。
Design guide: PDF
電路圖: PDF
參考設計

PMP40500 — 54-VDC 輸入、12-V 42-A 輸出半橋參考設計

此 12-V、42-A 輸出半橋式參考設計適合有線網路園區與分公司交換器中的匯流排轉換器。此設計具高效率及各種故障保護 (過電流和短路)。設計採用 3 kVRMS 基本及功能隔離式閘極驅動器 UCC21220D、UCC21220AD、UCC21222D，及 5.7-kRMS 強化隔離式閘極驅動器 UCC21540D、UCC21540DWK 及 UCC21541DW 以提供效率比較。
Test report: PDF
電路圖: PDF
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SOIC (DW) 16 Ultra Librarian
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