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Wireless communications test

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Block diagram

Wireless communications test

Block diagram

Overview

Wireless communication test equipment (WCTE) use configurable radio frequency (RF) front end to test wireless devices to ensure compliance with multiple standards. Our integrated circuits and reference designs help you create a WCTE signal chain that has a high level of integration and low power as channel count increases.

Design requirements

    Modern wireless communications test designs require:

  • Direct RF sampling data converters with wide bandwidth and high dynamic range.
  • Low-jitter multichannel JESD204B-compliant clock distribution.
  • Efficient power supply that minimizes board area and improves thermal performance.
  • Low EMI power supply that improves system sensitivity and dynamic range.
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Block diagram

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Wireless communications test

External clock Externalclock RF ports RFports Ext trigger Ext trigger Wired interface Wired interface USB USB DVI/VGA/HDMI DVI/VGA/HDMI LAN LAN IEEE-488 IEEE-488 Wireless interface Wireless interface Wi-Fi Wi-Fi Digital processing Digital processing FPGA FPGA System processor (Arm+DSP) System processor(Arm+DSP) Input user interface Input user interface Touch screen Touchscreen Knob & key pad Knob &key pad Push button Ctrl Push button Ctrl RF front end RF front end High speed ADC High speedADC RF amp RFamp High speed DAC High speedDAC Triggering Triggering Port calibration Port calibration Amp Amp Mixer Mixer VGA VGA IQ demod IQdemod IQ mod IQmod Amp Amp VGA VGA RF amp RFamp Mixer Mixer Pwr det Pwrdet LO LO REF REF Precision ADC PrecisionADC Precision DAC PrecisionDAC Signal input/output protection Signal input/output protection ESD protection ESD protection Signal isolation Signal isolation Digital isolators Digital isolators Self diagnostics/monitoring Self diagnostics/monitoring Precision ADC PrecisionADC DAC DAC Amp Amp Amp Amp Sensor Sensor Sensor Sensor Isolated AC/DC power supply Isolated AC/DC power supply Offline and isolated DC/DC controllers & converters Offline and isolatedDC/DC controllers& converters Input power protection Input power protection eFuse eFuse Non-isolated DC/DC power supply Non-isolated DC/DC power supply DC/DC DC/DC LDO LDO PMIC PMIC Supervisor Supervisor Sequencer Sequencer Power FETs Power FETs Memory Memory DDR termination regulator DDR terminationregulator Output user interface Output user interface Display Display Speaker Speaker LEDs LEDs Buzzer Buzzer Clocking Clocking Input buffer Inputbuffer PLL PLL Jitter cleaner Jittercleaner Clock distribution Clockdistribution

Clocking

close

High speed clocking systems require the lowest possible clock phase noise for the best signal chain performance and dynamic range. Multichannel clocking also requires the ability for precision phase alignment to control the channel-to-channel skew.

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RF & microwave (6)
RF PLLs & synthesizers
  • LMX2492—500MHz to 14GHz wideband, low noise fractional-N PLL with ramp/chirp generation
    Data sheet: PDF | HTML
  • LMX2595—20-GHz wideband RF synthesizer with phase synchronization & JESD204B support
    Data sheet: PDF | HTML
  • LMX2820—22.6-GHz wideband RF synthesizer with phase synchronization, JESD and <5-µs frequency calibration
    Data sheet: PDF | HTML
  • LMX2594—15-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support
    Data sheet: PDF | HTML
  • LMX2581—3.76-GHz wideband frequency synthesizer with integrated VCO
    Data sheet: PDF | HTML
  • LMX2582—5.5-GHz high performance, wideband PLLatinum RF synthesizer
    Data sheet: PDF | HTML
Clocks & timing (20)
Clock jitter cleaners
  • LMK04816—Three input low-noise clock jitter cleaner with dual loop PLLs
    Data sheet: PDF | HTML
  • LMK04616—Ultra low-noise and low power JESD204B compliant clock jitter cleaner
    Data sheet: PDF | HTML
  • LMK04828—Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
    Data sheet: PDF | HTML
  • LMK04806—Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO
    Data sheet: PDF | HTML
  • LMK04803—Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO
    Data sheet: PDF | HTML
  • LMK04832—Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop
    Data sheet: PDF | HTML
Clock buffers
  • LMK1D1204—4-channel output LVDS 1.8-V buffer
    Data sheet: PDF | HTML
  • CDCE18005—5/10 outputs clock buffer with divider
    Data sheet: PDF | HTML
  • CDCLVD1204—Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer
    Data sheet: PDF | HTML
  • LMK00306—3.1-GHz differential clock buffer/level translator with 6 configurable outputs
    Data sheet: PDF | HTML
  • LMK00105—Ultra-low jitter LVCMOS fanout buffer/level translator with universal input and 5 outputs
    Data sheet: PDF | HTML
  • CDCV304—General purpose and PCI-X 1:4 LVCMOS clock buffer
    Data sheet: PDF | HTML
Clock generators
  • LMK03318—Ultra-low jitter clock generator family with single PLL
    Data sheet: PDF | HTML
  • CDCE62005—5/10 outputs clock generator/jitter cleaner with integrated dual VCO
    Data sheet: PDF | HTML
  • CDCM6208—2:8 ultra-low power, low jitter clock generator
    Data sheet: PDF | HTML
Real-time clocks (RTCs) & timers
  • LMC555—World’s smallest 555 timer with low power, high accuracy and a Fmax of 3MHz
    Data sheet: PDF | HTML
  • TPL5100—Nano-powered programmable timer with power gating functionality and MOS driver
    Data sheet: PDF | HTML
  • TPL5110—Nano-powered system timer with MOS driver and manual MOSFET power ON
    Data sheet: PDF | HTML
  • TPL5111—Ultra low power system timer (35 nA) for power gating in duty cycled applications
    Data sheet: PDF | HTML
Oscillators
  • LMK61E2—Ultra-low jitter, EEPROM programmable oscillator for medical imaging and test and measurement
    Data sheet: PDF | HTML
  • TIDA-00359—Clocking Solution Reference Design for GSPS ADCs
    Design guide: PDF Schematic: PDF
  • TIDA-00431—RF Sampling 4-GSPS ADC Reference Design with 8-GHz DC-Coupled Differential Amplifier
    Design guide: PDF Schematic: PDF
  • TIDA-00432—Synchronization of JESD204B Giga-Sample ADCs using Xilinx Platform for Phased Array Radar Systems
    Design guide: PDF Schematic: PDF
  • TIDA-00479—Optimal Clock Sources for GSPS ADCs Reference Design
    Design guide: PDF Schematic: PDF
  • TIDA-00626—9.8GHz RF CW Signal Generator Using Integrated Synthesizer With Spur Reduction Reference Design
    Design guide: PDF Schematic: PDF
  • TIDA-00826—50-Ohm 2-GHz Oscilloscope Front-end Reference Design
    Design guide: PDF Schematic: PDF
  • TIDA-010122—Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems
    Design guide: PDF Schematic: PDF
  • TIDA-010131—Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers
    Design guide: PDF Schematic: PDF
  • TIDA-010132—Multichannel RF transceiver reference design for radar applications
    Design guide: PDF Schematic: PDF
  • TIDA-01015—4 GHz Clock Reference Design for 12 Bit High Speed ADCs in Digital Oscilloscopes & Wireless Testers
    Design guide: PDF Schematic: PDF
  • TIDA-01016—Clocking Reference Design for RF Sampling ADCs in Signal Analyzers and Wireless Testers
    Design guide: PDF Schematic: PDF
  • TIDA-01017—High Speed Multi-Channel ADC Clock Reference Design for Oscilloscopes, Wireless Testers and Radars
    Design guide: PDF Schematic: PDF
  • TIDA-01021—Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
    Design guide: PDF Schematic: PDF Schematic: PDF
  • TIDA-01022—Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
    Design guide: PDF | HTML Schematic: PDF
  • TIDA-01023—High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers
    Design guide: PDF Schematic: PDF Schematic: PDF
  • TIDA-01024—High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers
    Design guide: PDF Schematic: PDF Schematic: PDF
  • TIDA-01346—Multiple PLL combination reference design for <40-fs jitter (100-Hz to 100-MHz)
    Design guide: PDF Schematic: PDF

Technical documentation

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Type Title Date
White paper Analog advancements make waves in 5G communications 12 Aug 2016

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