A bypass capacitor is used to minimize high frequency noise into the supply pin of the DRV device. TI recommends placing capacitors as close as possible to the power input pins of the device and ground pins. If the trace lengths between the bypass capacitor and the device are not minimized, they can be inductive at the high frequencies that the bypass capacitor is meant to filter. The added impedance from trace inductance can cause ringing in the voltage or current at the supply pin which contributes to EMI and affects the performance of digital or analog circuits. A best practice is to place the capacitor with the lesser value as close as possible to the device to minimize the influence of the inductance of the trace. Connect larger-value capacitors after the smaller ones because as the value of the capacitor increases the inductance becomes more negligible.

Figure 5-4 Decoupling Capacitors Close to Device

As Section 3.2 shows, the more vias used, the lower the impedance. TI highly recommends using multiple vias at the power and ground layers. Placing vias directly on the mounting pads of the capacitor can be an effective way to minimize the routing area and still achieve the current flow routing. Follow these guidelines for bypass capacitors:

• Do not use vias between the bypass capacitors and the active device. Visualize the high-frequency current flow and reduce loops of high-frequency current as much as possible.
• Make sure bypass capacitors are on the same layer as active components for best results. Do not place a via between the bypass capacitor pin and the IC supply or ground pin.
• Route vias into the bypass capacitors and then into the active component.
• Use the most vias and the widest traces for the best layout.
• The closer the bypass capacitor, the better (less than 0.5 cm, 0.2 in)
• Do not use a length-to-width ratio that is greater than 3:1.

Figure 5-5 shows an example of good and bad bypassing.

Figure 5-5 Bypass Capacitor Placement