The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a
solution for secure distribution of content-protected digital video within automotive entertainment
systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed
serialized interface. The digital video data is protected using the industry standard HDCP copy
protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission
and full duplex control including I2C communication over a single differential link. Consolidation
of video data and control over a single differential pair reduces the interconnect size and weight,
while also eliminating skew issues and simplifying system design.
The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level
shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are
serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and
randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are
stored in on-chip memory.
Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local
output pin.
The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a
solution for secure distribution of content-protected digital video within automotive entertainment
systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed
serialized interface. The digital video data is protected using the industry standard HDCP copy
protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission
and full duplex control including I2C communication over a single differential link. Consolidation
of video data and control over a single differential pair reduces the interconnect size and weight,
while also eliminating skew issues and simplifying system design.
The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level
shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are
serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and
randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are
stored in on-chip memory.
Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local
output pin.