Startseite Energiemanagement Linear- und Low-Dropout-Regler (LDO)
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Energiemanagement
Linear- und Low-Dropout-Regler (LDO)

TPS732

AKTIV

Hochpräziser Ultra-Low-Drop-Out-Spannungsregler, 250 mA, mit Gegenstromschutz und Aktivierung

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Datenblatt

TPS732

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Output options Adjustable Output, Fixed Output Iout (max) (A) 0.25 Vin (max) (V) 5.5 Vin (min) (V) 1.7 Vout (max) (V) 5.5 Vout (min) (V) 1.2 Fixed output options (V) 1.3, 1.5, 1.6, 1.8, 1.9, 2.5, 3, 3.3, 5 Rating Catalog Noise (µVrms) 30 PSRR at 100 KHz (dB) 32 Iq (typ) (mA) 0.4 Thermal resistance θJA (°C/W) 53 Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Foldback Overcurrent protection, Reverse Current Protection Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 40 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 0.25 Vin (max) (V) 5.5 Vin (min) (V) 1.7 Vout (max) (V) 5.5 Vout (min) (V) 1.2 Fixed output options (V) 1.3, 1.5, 1.6, 1.8, 1.9, 2.5, 3, 3.3, 5 Rating Catalog Noise (µVrms) 30 PSRR at 100 KHz (dB) 32 Iq (typ) (mA) 0.4 Thermal resistance θJA (°C/W) 53 Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Foldback Overcurrent protection, Reverse Current Protection Accuracy (%) 1 Dropout voltage (Vdo) (typ) (mV) 40 Operating temperature range (°C) -40 to 125
SOT-223 (DCQ) 6 45.89 mm² 6.5 x 7.06 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 VSON (DRB) 8 9 mm² 3 x 3
  • Stable with no output capacitor or any value or type of capacitor
  • Input voltage range: 1.7V to 5.5V
  • Ultra-low dropout voltage: 40mV typical at 250mA
  • Excellent load transient response—with or without optional output capacitor
  • NMOS topology provides low reverse leakage current
  • Low noise: 30µVRMS typical (10kHz to 100kHz)
  • 0.5% initial accuracy
  • 1% overall accuracy (line, load, and temperature)
  • Less than 1µA maximum IQ in shutdown mode
  • Thermal shutdown and specified min and max current limit protection
  • Available in multiple output voltage versions:
    • Fixed outputs of 1.2V to 5V
    • Adjustable outputs from 1.2V to 5.5V
    • Custom outputs available
  • Stable with no output capacitor or any value or type of capacitor
  • Input voltage range: 1.7V to 5.5V
  • Ultra-low dropout voltage: 40mV typical at 250mA
  • Excellent load transient response—with or without optional output capacitor
  • NMOS topology provides low reverse leakage current
  • Low noise: 30µVRMS typical (10kHz to 100kHz)
  • 0.5% initial accuracy
  • 1% overall accuracy (line, load, and temperature)
  • Less than 1µA maximum IQ in shutdown mode
  • Thermal shutdown and specified min and max current limit protection
  • Available in multiple output voltage versions:
    • Fixed outputs of 1.2V to 5V
    • Adjustable outputs from 1.2V to 5.5V
    • Custom outputs available

The TPS732 low-dropout (LDO) voltage regulator uses an NMOS pass transistor in a voltage-follower configuration. This topology is stable using output capacitors with low equivalent series resistance (ESR), and even allows operation without a capacitor. The device also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current.

The TPS732 uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is less than 1µA and designed for portable applications. The extremely low output noise (30µVRMS with 0.1µF CNR) is designed for powering VCOs. This device is protected by thermal shutdown and foldback current limit.

The TPS732 low-dropout (LDO) voltage regulator uses an NMOS pass transistor in a voltage-follower configuration. This topology is stable using output capacitors with low equivalent series resistance (ESR), and even allows operation without a capacitor. The device also provides high reverse blockage (low reverse current) and ground pin current that is nearly constant over all values of output current.

The TPS732 uses an advanced BiCMOS process to yield high precision while delivering very low dropout voltages and low ground pin current. Current consumption, when not enabled, is less than 1µA and designed for portable applications. The extremely low output noise (30µVRMS with 0.1µF CNR) is designed for powering VCOs. This device is protected by thermal shutdown and foldback current limit.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet TPS732 Capacitor-Free, NMOS, 250mA, Low-Dropout Regulator With Reverse Current Protection datasheet (Rev. Q) PDF | HTML 10 Sep 2024
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 Aug 2020
Technical article LDO Basics: Thermals – How hot is your application? PDF | HTML 20 Sep 2017
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 Aug 2017
User guide TPS73x01DRBEVM-518 User's Guide 13 Aug 2009
User guide DEM-SOT223LDO Demonstration Fixture 15 Okt 2003
More literature DMOS Delivers Dramatic Performance Gains to LDO Regulators (EDN mag) 14 Feb 2001

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

DEM-SOT223LDO — DEM-SOT223LDO-kompatibel mit den meisten LDOs mit positivem Ausgang im SOT223 (DCQ)-Gehäuse

The Texas Instruments DEM-SOT223LDO demonstration module (DEM) helps designers evaluate the operation and performance of Texas Instruments low-dropout regulators (LDOs).  This module is compatible with most positive output LDOs offered in the SOT223 (DCQ) package.

Benutzerhandbuch: PDF
Nicht verfügbar auf TI.com
Evaluierungsplatine

TPS73201DRBEVM-518 — TPS73201DRBEVM-518-Evaluierungsmodul

The TPS73201DRBEVM-518 evaluation module is a fully assembled and tested circuit for evaluating the TPS73201 low-dropout (LDO) voltage regulator in the DRB (3x3mm SON) package.
Benutzerhandbuch: PDF
Nicht verfügbar auf TI.com
Simulationsmodell

TPS73201 PSpice Transient Model (Rev. A)

SBVM171A.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73201 Unencrypted PSpice Transient Model

SBVM600.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73213 PSpice Transient Model

SBVM369.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73213 Unencrypted PSpice Transient Model

SBVM596.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73215 PSpice Transient Model

SBVM370.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73215 Unencrypted PSpice Transient Model

SBVM598.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73216 PSpice Transient Model

SBVM373.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73216 Unencrypted PSpice Transient Model

SBVM599.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73218 PSpice Transient Model

SBVM374.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73218 Unencrypted PSpice Transient Model

SBVM602.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73219 PSpice Transient Model

SBVM375.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73219 Unencrypted PSpice Transient Model

SBVM594.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73225 PSpice Transient Model

SBVM376.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73225 Unencrypted PSpice Transient Model

SBVM593.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73230 PSpice Transient Model

SBVM372.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73230 Unencrypted PSpice Transient Model

SBVM597.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73233 PSpice Transient Model

SBVM371.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73233 Unencrypted PSpice Transient Model

SBVM601.ZIP (1 KB) - PSpice Model
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Simulationsmodell

TPS73250 PSpice Transient Model

SBVM363.ZIP (21 KB) - PSpice Model
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Simulationsmodell

TPS73250 TINA-TI Transient Reference Design

SBVM366.TSC (49 KB) - TINA-TI Reference Design
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Simulationsmodell

TPS73250 TINA-TI Transient Spice Model

SBVM365.ZIP (7 KB) - TINA-TI Spice Model
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Simulationsmodell

TPS73250 Unencrypted PSpice Transient Model

SBVM595.ZIP (1 KB) - PSpice Model
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Schaltplan

5Vin Power Design using Integrated-FET DCDC Converters and LDO's

SLVR326.PDF (1176 KB)
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Schaltplan

12Vin Power Design using Integrated-FET DCDC Converters and LDO's

SLVR327.PDF (1160 KB)
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Schaltplan

5Vin Power Design using Integrated-FET DCDC Converters and a LDO (Rev. A)

SLVR328A.PDF (938 KB)
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Schaltplan

12Vin Power Design using Integrated-FET DCDC Converters and a LDO (Rev. A)

SLVR329A.PDF (932 KB)
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Referenzdesigns

TIDA-00661 — Hochauflösendes, schnell anlaufendes analoges Frontend für offene Leistungsschalter – Referenzdesign

The TIDA-00661 reference design features signal processing front-end subsystem for electronic trip units (ETU) used in air circuit breakers (ACB) or molded case circuit breakers (MCCB). This subsystem consists of Delta-Sigma ADC with 24-Bit resolution and fast startup (< 3ms), ±2.5V (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00306 — Referenzdesign für 100BASE-FX- oder 1000BASE-X-Medienwandler mit Kupfer-Glasfaser-Schnittstelle für

This reference design details a methodology to use the DP83849 evaluation board to implement a 10/100BASE-TX to 10/100BASE-FX media converter, which enables copper based legacy equipment to be easily connected to a fiber network. Copper based Ethernet (10/100BASE-TX) has been widely used in grid (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

PMP21887 — Referenzdesign für statische 600-A-/360-A-Spitzenkern-PMBus-Spannung mit 12 Phasen für ASICs

This reference design is a a 12-phase power management bus (PMBus) buck converter powering datacenter hardware accelerator, enterprise switch and router application-specific integrated circuit (ASIC) core rails. It provides 360 A of continuous current and 600 A of peak current at 0.85-V nominal (...)
Test report: PDF
Schaltplan: PDF
Referenzdesigns

PMP20489 — Kompaktes 12 Vin, 0,8 V, 200 A und 3,3 V, 75 A, POL-Referenzdesign

The TPS53679-based reference design provides a single IC for control of two multi-phase outputs with up to 6 phases on main output and up to 2 phases on channel 2; up to 7 phases in all.  Multi-phase also allows output ripple cancellation and effective higher bandwidth control for a (...)
Test report: PDF
Schaltplan: PDF
Referenzdesigns

PMP2187 — Flyback-Linearregler für Medical Pack (5,75 V bei 10 mA) – Referenzdesign

Dieses Design bietet isolierte Ausgänge mit 5 V (x2), 3,3 V, 2,5 V und -5 V. Alle Ausgänge sind rauschgefiltert mit Low Dropout (LDO)-Linearreglern für rauschempfindliche Anwendungen wie medizinische Bildgebung und Datenerfassung.
Test report: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00826 — 50-Ohm-2-GHz-Oszilloskop-Frontend – Referenzdesign

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
SOT-223 (DCQ) 6 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
VSON (DRB) 8 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

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  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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