Startseite Energiemanagement Linear- und Low-Dropout-Regler (LDO)
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Energiemanagement
Linear- und Low-Dropout-Regler (LDO)

TPS74301

AKTIV

Hochpräziser, einstellbarer Spannungsregler mit extrem niedriger Dropout-Spannung 1,5 A, niedriger V

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Datenblatt

TPS74301

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Output options Adjustable Output, Tracking Output Iout (max) (A) 1.5 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Noise (µVrms) 20 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 20 Rating Catalog Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 1 PSRR at 100 KHz (dB) 45 Dropout voltage (Vdo) (typ) (mV) 55 Operating temperature range (°C) -40 to 85
Output options Adjustable Output, Tracking Output Iout (max) (A) 1.5 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Noise (µVrms) 20 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 20 Rating Catalog Load capacitance (min) (µF) 0 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 1 PSRR at 100 KHz (dB) 45 Dropout voltage (Vdo) (typ) (mV) 55 Operating temperature range (°C) -40 to 85
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGW) 20 25 mm² 5 x 5
  • Track Pin Allows for Flexible Power-Up Sequencing
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.9V with External Bias Supply
  • Adjustable Output (0.8V to 3.6V)
  • Fixed Output (0.9V to 3.6V)
  • Ultra-Low Dropout: 55mV at 1.5A (typ)
  • Stable with Any or No Output Capacitor
  • Excellent Transient Response
  • Available in 5mm × 5mm × 1mm QFN and DDPAK-7 Packages
  • Open-Drain Power-Good (5 × 5 QFN)
  • Active High Enable
  • APPLICATIONS
    • FPGA Applications
    • DSP Core and I/O Voltages
    • Post-Regulation Applications
    • Applications with Special Start-Up Time or Sequencing Requirements

All other trademarks are the property of their respective owners
  • Track Pin Allows for Flexible Power-Up Sequencing
  • 1% Accuracy Over Line, Load, and Temperature
  • Supports Input Voltages as Low as 0.9V with External Bias Supply
  • Adjustable Output (0.8V to 3.6V)
  • Fixed Output (0.9V to 3.6V)
  • Ultra-Low Dropout: 55mV at 1.5A (typ)
  • Stable with Any or No Output Capacitor
  • Excellent Transient Response
  • Available in 5mm × 5mm × 1mm QFN and DDPAK-7 Packages
  • Open-Drain Power-Good (5 × 5 QFN)
  • Active High Enable
  • APPLICATIONS
    • FPGA Applications
    • DSP Core and I/O Voltages
    • Post-Regulation Applications
    • Applications with Special Start-Up Time or Sequencing Requirements

All other trademarks are the property of their respective owners

The TPS743xx low-dropout (LDO) linear regulators provide an easy-to-use robust power management solution for a wide variety of applications. The TRACK pin allows the output to track an external supply. This feature is useful in minimizing the stress on ESD structures that are present between the CORE and I/O power pins of many processors. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors and the family is fully specified from –40°C to +125°C. The TPS743xx is offered in a small (5mm × 5mm) QFN package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available.

The TPS743xx low-dropout (LDO) linear regulators provide an easy-to-use robust power management solution for a wide variety of applications. The TRACK pin allows the output to track an external supply. This feature is useful in minimizing the stress on ESD structures that are present between the CORE and I/O power pins of many processors. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors and the family is fully specified from –40°C to +125°C. The TPS743xx is offered in a small (5mm × 5mm) QFN package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet 1.5A Ultra-LDO with Programmable Sequencing datasheet (Rev. K) 10 Aug 2010
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 Aug 2020
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 Jun 2019
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 21 Mär 2018
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 Aug 2017
Application note Using New Thermal Metrics 15 Dez 2009
Analog Design Journal Q3 2007 Issue Analog Applications Journal 10 Aug 2007
Analog Design Journal Simultaneous power-down sequencing with the TPS74x01 family of linear regulators 10 Aug 2007
Analog Design Journal A 3-A, 1.2-Vout linear regulator with 80% efficiency and Plost < 1W 10 Okt 2006
EVM User's guide TPS74x01EVM-118 User's Guide 20 Jun 2006

Design und Entwicklung

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Evaluierungsplatine

TPS74301EVM-118 — TPS74301-Evaluierungsmodul

The TPS74301EVM-118 evaluation module (EVM) is designed to help the user easily evaluate and test the operation and functionality of the TPS74301 LDO linear regulator. The EVM uses the TPS74301, 1.5 A linear regulator with tracking and integrated power good (PG). Refer to the (...)

Benutzerhandbuch: PDF
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Simulationsmodell

TPS74301 PSpice Transient Model (Rev. B)

SLIM015B.ZIP (62 KB) - PSpice Model
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Simulationsmodell

TPS74301 TINA-TI Transient Reference Design

SLIM287.TSC (105 KB) - TINA-TI Reference Design
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Simulationsmodell

TPS74301 TINA-TI Transient Spice Model

SLIM286.ZIP (36 KB) - TINA-TI Spice Model
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Simulationsmodell

TPS74301 Unencrypted PSpice Transient Model

SBVM635.ZIP (2 KB) - PSpice Model
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Schaltplan

5Vin Solution with 1.5-A Core Supply (Rev. A)

SLVR303A.PDF (196 KB)
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Schaltplan

5V/12V Input DM6467 (x2) Power Ref Design Using a DCDC Controller & Converter

SLVR337.PDF (158 KB)
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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TO-263 (KTW) 7 Ultra Librarian
VQFN (RGW) 20 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

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