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UCC27512-EP

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Verbessertes Produkt 4-A/8-A Einkanal-Gate-Treiber mit 5-V-UVLO-Eingang SON-Gehäuse

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Datenblatt

UCC27512-EP

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Produktdetails

Number of channels 1 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 8 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Hysteretic Logic Operating temperature range (°C) -55 to 125 Rise time (ns) 9 Fall time (ns) 7 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating HiRel Enhanced Product Undervoltage lockout (typ) (V) 4 Driver configuration Inverting, Non-Inverting
Number of channels 1 Power switch GaNFET, IGBT, MOSFET Peak output current (A) 8 Input supply voltage (min) (V) 4.5 Input supply voltage (max) (V) 18 Features Hysteretic Logic Operating temperature range (°C) -55 to 125 Rise time (ns) 9 Fall time (ns) 7 Propagation delay time (µs) 0.013 Input threshold CMOS, TTL Channel input logic Inverting, Non-Inverting Input negative voltage (V) 0 Rating HiRel Enhanced Product Undervoltage lockout (typ) (V) 4 Driver configuration Inverting, Non-Inverting
WSON (DRS) 6 9 mm² 3 x 3
  • Low-Cost, Gate-Driver Device Offering Superior Replacement
    of NPN and PNP Discrete Solutions
  • 4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
  • Strong Sink Current Offers Enhanced Immunity Against Miller Turn On
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (9-ns and 7-ns typical)
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (ensures glitch free operation at
    power-up and power-down)
  • TTL and CMOS Compatible Input Logic Threshold,
    (independent of supply voltage)
  • Hysteretic Logic Thresholds for High Noise Immunity
  • Dual Input Design (choice of an inverting (IN- pin) or non-inverting
    (IN+ pin) driver configuration)
    • Unused Input Pin can be Used for Enable or Disable Function
  • Output Held Low when Input Pins are Floating
  • Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin
    Bias Supply Voltage
  • 6-Pin DRS (3mm × 3 mm WSON with exposed thermal pad) Package

Supports Defense, Aerospace, and Medical Applications

  • Controlled Baseline
  • One Assembly and Test Site
  • One Fabrication Site
  • Available in Military (–55°C to 125°C) Temperature Range
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability
  • Low-Cost, Gate-Driver Device Offering Superior Replacement
    of NPN and PNP Discrete Solutions
  • 4-A Peak Source and 8-A Peak Sink Asymmetrical Drive
  • Strong Sink Current Offers Enhanced Immunity Against Miller Turn On
  • Fast Propagation Delays (13-ns typical)
  • Fast Rise and Fall Times (9-ns and 7-ns typical)
  • 4.5-V to 18-V Single Supply Range
  • Outputs Held Low During VDD UVLO (ensures glitch free operation at
    power-up and power-down)
  • TTL and CMOS Compatible Input Logic Threshold,
    (independent of supply voltage)
  • Hysteretic Logic Thresholds for High Noise Immunity
  • Dual Input Design (choice of an inverting (IN- pin) or non-inverting
    (IN+ pin) driver configuration)
    • Unused Input Pin can be Used for Enable or Disable Function
  • Output Held Low when Input Pins are Floating
  • Input Pin Absolute Maximum Voltage Levels Not Restricted by VDD Pin
    Bias Supply Voltage
  • 6-Pin DRS (3mm × 3 mm WSON with exposed thermal pad) Package

Supports Defense, Aerospace, and Medical Applications

  • Controlled Baseline
  • One Assembly and Test Site
  • One Fabrication Site
  • Available in Military (–55°C to 125°C) Temperature Range
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability

The UCC27512 single-channel, high-speed, low-side gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27512 is capable of sourcing and sinking high, peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns.

The UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turn-on effect.

UCC27512 is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of –55°C to 125°C. Internal Under Voltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best in class switching characteristics, is especially suited for driving emerging wide band-gap power switching devices such as GaN power semiconductor devices.

The UCC27512 single-channel, high-speed, low-side gate driver device is capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27512 is capable of sourcing and sinking high, peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay typically 13 ns.

The UCC27512 provides 4-A source, 8-A sink (asymmetrical drive) peak-drive current capability. Strong sink capability in asymmetrical drive boosts immunity against parasitic, Miller turn-on effect.

UCC27512 is designed to operate over a wide VDD range of 4.5 V to 18 V and wide temperature range of –55°C to 125°C. Internal Under Voltage Lockout (UVLO) circuitry on VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best in class switching characteristics, is especially suited for driving emerging wide band-gap power switching devices such as GaN power semiconductor devices.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet Single Channel High-Speed, Low-Side Gate Driver (With 4-A/8-A Peak Source/Sink). datasheet 10 Jun 2013
* Radiation & reliability report UCC27512MDRSTEP Reliability Report 09 Feb 2016
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020

Design und Entwicklung

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