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THS6062

ACTIVO

Receptor diferencial doble ADSL de bajo ruido

Detalles del producto

Number of channels 2 Architecture DSL Line Driver Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 33 BW at Acl (MHz) 100 Acl, min spec gain (V/V) 1 Vn at flatband (typ) (nV√Hz) 1.6 Vn at 1 kHz (typ) (nV√Hz) 1.9 Iq per channel (typ) (mA) 7.5 Vos (offset voltage at 25°C) (max) (mV) 6 Rail-to-rail No Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 95 Input bias current (max) (pA) 10000000 Offset drift (typ) (µV/°C) 20 GBW (typ) (MHz) 100 Iout (typ) (mA) 90 2nd harmonic (dBc) 91 3rd harmonic (dBc) 109 Frequency of harmonic distortion measurement (MHz) 1
Number of channels 2 Architecture DSL Line Driver Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 33 BW at Acl (MHz) 100 Acl, min spec gain (V/V) 1 Vn at flatband (typ) (nV√Hz) 1.6 Vn at 1 kHz (typ) (nV√Hz) 1.9 Iq per channel (typ) (mA) 7.5 Vos (offset voltage at 25°C) (max) (mV) 6 Rail-to-rail No Rating Catalog Operating temperature range (°C) -40 to 85 CMRR (typ) (dB) 95 Input bias current (max) (pA) 10000000 Offset drift (typ) (µV/°C) 20 GBW (typ) (MHz) 100 Iout (typ) (mA) 90 2nd harmonic (dBc) 91 3rd harmonic (dBc) 109 Frequency of harmonic distortion measurement (MHz) 1
HVSSOP (DGN) 8 14.7 mm² 3 x 4.9 SOIC (D) 8 29.4 mm² 4.9 x 6
  • ADSL Differential Receiver
  • Low 1.6 nV/)
  • 5 V, ±5 V to ±15 V Typical Operation
  • Available in Standard SOIC or MSOP PowerPAD™ Package
  • PowerPAD is a trademark of Texas Instruments.

    • ADSL Differential Receiver
    • Low 1.6 nV/)
  • 5 V, ±5 V to ±15 V Typical Operation
  • Available in Standard SOIC or MSOP PowerPAD™ Package
  • PowerPAD is a trademark of Texas Instruments.

    The THS6062 is a high-speed differential receiver designed for ADSL data communication systems. Its very low 1.6 nV/), exceeding the distortion requirements of ADSL CODECs. The THS6062 is a voltage feedback amplifier offering a high 100-MHz bandwidth and 100-V/µs slew rate and is stable at gains of 2(-1) or greater. It operates over a wide range of power supply voltages including 5 V and ±5 V to ±15 V. This device is available in standard SOIC or MSOP PowerPAD package. The small, surface-mount, thermally-enhanced MSOP PowerPAD package is fully compatible with automated surface-mount assembly procedures.

    The THS6062 is a high-speed differential receiver designed for ADSL data communication systems. Its very low 1.6 nV/), exceeding the distortion requirements of ADSL CODECs. The THS6062 is a voltage feedback amplifier offering a high 100-MHz bandwidth and 100-V/µs slew rate and is stable at gains of 2(-1) or greater. It operates over a wide range of power supply voltages including 5 V and ±5 V to ±15 V. This device is available in standard SOIC or MSOP PowerPAD package. The small, surface-mount, thermally-enhanced MSOP PowerPAD package is fully compatible with automated surface-mount assembly procedures.

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    Documentación técnica

    star =Principal documentación para este producto seleccionada por TI
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    Tipo Título Fecha
    * Data sheet Low-Noise ADSL Dual Differential Receiver datasheet (Rev. D) 15 oct 2007
    E-book The Signal e-book: A compendium of blog posts on op amp design topics 28 mar 2017
    Application note Noise Analysis for High Speed Op Amps (Rev. A) 17 ene 2005
    Application note Active Output Impedance for ADSL Line Drivers 26 nov 2002
    User guide THS6062 EVM User's Guide 21 ene 1999

    Diseño y desarrollo

    Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

    Modelo de simulación

    THS6062 PSpice Model (Rev. B)

    SLOJ011B.ZIP (39 KB) - PSpice Model
    Modelo de simulación

    THS6062 TINA-TI Reference Design (Rev. B)

    SLAC108B.TSC (98 KB) - TINA-TI Reference Design
    Modelo de simulación

    THS6062 TINA-TI Spice Model (Rev. A)

    SLAM037A.ZIP (4 KB) - TINA-TI Spice Model
    Herramienta de simulación

    PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

    PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Herramienta de simulación

    TINA-TI — Programa de simulación analógica basado en SPICE

    TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
    Guía del usuario: PDF
    Encapsulado Pines Símbolos CAD, huellas y modelos 3D
    HVSSOP (DGN) 8 Ultra Librarian
    SOIC (D) 8 Ultra Librarian

    Pedidos y calidad

    Información incluida:
    • RoHS
    • REACH
    • Marcado del dispositivo
    • Acabado de plomo/material de la bola
    • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
    • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
    • Contenido del material
    • Resumen de calificaciones
    • Monitoreo continuo de confiabilidad
    Información incluida:
    • Lugar de fabricación
    • Lugar de ensamblaje

    Soporte y capacitación

    Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

    El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

    Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

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