DS90UR124
- Supports displays with 18-bit color depth
- 5MHz to 43MHz Pixel clock
- Automotive-grade product AEC-Q100 grade 2 qualified
- 24:1 Interface compression
- Embedded clock with DC balancing supports AC-coupled data transmission
- Capable to drive up to 10 meters shielded twisted-pair cable
- No reference clock required (deserializer)
- Meets ISO 10605 ESD – greater than 8kV HBM ESD structure
- Hot plug support
- EMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs
- @Speed BIST (Built-In Self-Test) to validate LVDS transmission path
- Individual power-down controls for both transmitter and receiver
- Power supply range 3.3V ±10%
- 48-pin TQFP package for transmitter and 64-pin TQFP package for receiver
- Temperature range: –40°C to 105°C
- Backward-compatible mode with DS90C241/DS90C124
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90URxxx-Q1 5MHz to 43MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset datasheet (Rev. P) | PDF | HTML | 2024年 8月 29日 |
| Application note | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013年 4月 29日 | ||
| Application note | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013年 4月 29日 | ||
| Application note | AN-1807 FPD-Link II Display SerDes Overview (Rev. B) | 2013年 4月 26日 | ||
| Application note | AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B) | 2013年 4月 26日 | ||
| Application note | Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) | 2013年 4月 26日 | ||
| User guide | High Efficiency Portable Media Player (PMP) Dock Station User Guide | 2012年 1月 27日 | ||
| User guide | DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide | 2012年 1月 26日 | ||
| User guide | FPD to SERDES (UR) Translator Chip DS99R421 Evaluation Kit User's Guide | 2012年 1月 26日 |
設計與開發
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SERDESUR-43USB — 適用於 DS90UR241 DS90UR124 串聯器和解串器晶片組的評估套件
The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.
The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFP (PAG) | 64 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。