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隔離式閘極驅動器

ISO5852S-EP

現行

具有分離輸出、主動保護功能的 5.7kVrms、2.5A/5A 強化型單通道絕緣式閘極驅動器

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產品規格表

ISO5852S-EP

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 2121 Transient isolation voltage (VIOTM) (VPK) 8000 Power switch IGBT, MOSFET, SiCFET Peak output current (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (max) (V) 30 Output VCC/VDD (min) (V) 15 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
Number of channels 1 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 2121 Transient isolation voltage (VIOTM) (VPK) 8000 Power switch IGBT, MOSFET, SiCFET Peak output current (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (max) (V) 30 Output VCC/VDD (min) (V) 15 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • 100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at VCM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –55°C to +125°C Ambient
  • Surge Immunity 12800-VPK (according to IEC 61000-4-5)
  • Safety-Related Certifications:
    • 8000-VPK VIOTM and 2121-VPK VIORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-VRMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950-1, IEC 60601-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
    • All Certifications Complete per UL, VDE, CQC, TUV and Planned for CSA
  • 100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at VCM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –55°C to +125°C Ambient
  • Surge Immunity 12800-VPK (according to IEC 61000-4-5)
  • Safety-Related Certifications:
    • 8000-VPK VIOTM and 2121-VPK VIORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-VRMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950-1, IEC 60601-1 and IEC 61010-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
    • All Certifications Complete per UL, VDE, CQC, TUV and Planned for CSA

The ISO5852S-EP device is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15-V to maximum 30-V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, VEE2, the gate-driver output is pulled hard to the VEE2 potential which turns the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S-EP device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –55°C to +125°C ambient.

The ISO5852S-EP device is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15-V to maximum 30-V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, VEE2, the gate-driver output is pulled hard to the VEE2 potential which turns the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S-EP device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –55°C to +125°C ambient.
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類型 標題 日期
* Data sheet ISO5852S-EP High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features datasheet PDF | HTML 2016年 12月 23日
* Radiation & reliability report ISO5852SMDWREP Reliability Report 2017年 4月 20日
User guide UCC217xx and ISO5x5x Half-Bridge EVM User's Guide for Wolfspeed 1200-V SiC 2023年 9月 1日
Application note Comparative Analysis of Two Different Methods for Gate-Drive Current Boosting (Rev. A) PDF | HTML 2022年 2月 17日
Application brief External Gate Resistor Selection Guide (Rev. A) 2020年 2月 28日
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020年 2月 28日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ISO5852SEVM — 強化型隔離式 IGBT 閘極驅動器評估模組

This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.

使用指南: PDF
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模擬型號

ISO5852S IBIS Model

SLLM283.ZIP (33 KB) - IBIS Model
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模擬型號

ISO5852S PSpice Transient Model (Rev. A)

SLLM300A.ZIP (232 KB) - PSpice Model
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模擬型號

ISO5852S Unencrypted PSPICE Transient Model

SLLM446.ZIP (4 KB) - PSpice Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 16 Ultra Librarian
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