PCA9557
- Low standby current consumption of 1µA maximum
- I2C to parallel port expander
- Operating power-supply voltage range of 2.3V to 5.5V
- 5V Tolerant I/O ports
- 400kHz Fast I2C bus
- Three hardware address pins allow for use of up to eight devices on I2C/SMBus
- Lower-voltage higher-performance migration path for PCA9556
- Input and output configuration register
- Polarity inversion register
- Active-low reset input
- Internal power-on reset
- High-impedance open drain on P0
- Power up with all channels configured as inputs
- No glitch on power up
- Noise filter on SCL or SDA inputs
- Latched outputs with high current drive maximum capability for directly driving LEDs
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 2000V Human-body model (A114-A)
- 200V Machine model (A115-A)
- 1000V Charged-device model (C101)
This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3V to 5.5V VCC operation. The device provides general-purpose remote I/O expansion for most microcontroller families through the I2C interface [serial clock (SCL) and serial data (SDA)].
The PCA9557 consists of one 8-bit configuration (input or output selection), input port, output port, and polarity inversion (active-high) registers. At power on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system controller.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption.
The system controller can reset the PCA9557 in the event of a timeout or other improper operation by asserting a low in the active-low reset (RESET) input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, allowing up to eight devices to share the same I2C bus or SMBus.
技術文件
設計與開發
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I2C-DESIGNER — I2C 設計工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 16 | Ultra Librarian |
SSOP (DB) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
TVSOP (DGV) | 16 | Ultra Librarian |
VQFN (RGV) | 16 | Ultra Librarian |
VQFN (RGY) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。