PCA9557
- Low Standby Current Consumption of 1 μA Max
- I2C to Parallel Port Expander
- Operating Power-Supply Voltage Range of 2.3 V to 5.5 V
- 5-V Tolerant I/O Ports
- 400-kHz Fast I2C Bus
- Three Hardware Address Pins Allow for Use of up to Eight Devices on I2C/SMBus
- Lower-Voltage Higher-Performance Migration Path for PCA9556
- Input/Output Configuration Register
- Polarity Inversion Register
- Active-Low Reset Input
- Internal Power-On Reset
- High-Impedance Open Drain on P0
- Power Up With All Channels Configured as Inputs
- No Glitch on Power Up
- Noise Filter on SCL/SDA Inputs
- Latched Outputs With High Current Drive Maximum Capability for Directly Driving LEDs
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
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This 8-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 2.3-V to 5.5-V VCC operation. The device provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL) and serial data (SDA)].
The PCA9557 consists of one 8-bit configuration (input or output selection), input port, output port, and polarity inversion (active-high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption.
The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting a low in the active-low reset (RESET) input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part.
Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I2C address, allowing up to eight devices to share the same I2C bus or SMBus.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | PCA9557 Remote 8-Bit I2C and SMBus Low-Power I/O Expander datasheet (Rev. J) | 2014年 6月 12日 | |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024年 7月 3日 | |
| Application note | I2C Dynamic Addressing | 2019年 4月 25日 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Choosing the Correct I2C Device for New Designs | PDF | HTML | 2016年 9月 7日 | |
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| Application note | Understanding the I2C Bus | PDF | HTML | 2015年 6月 30日 | |
| Application note | Maximum Clock Frequency of I2C Bus Using Repeaters | 2015年 5月 15日 | ||
| Application note | I2C Bus Pull-Up Resistor Calculation | PDF | HTML | 2015年 2月 13日 | |
| Application note | Programming Fun Lights With TI's TCA6507 | 2007年 11月 30日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 |
設計與開發
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I2C-DESIGNER — I2C 設計工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| SSOP (DB) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
| TVSOP (DGV) | 16 | Ultra Librarian |
| VQFN (RGV) | 16 | Ultra Librarian |
| VQFN (RGY) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。