產品規格表
TCA9617B
- Two-channel bidirectional I2C buffer
- Support for standard mode, fast mode (400kHz), and fast mode+ (1MHz) I2C operation
- Operating supply voltage range of 0.8V to 5.5V on A-side
- Operating supply voltage range of 2.2V to 5.5V on B-side
- Voltage-level translation from 0.8V to 5.5V and 2.2V to 5.5V
- Footprint and function replacement for TCA9517
- Active-high repeater-enable input
- Open-drain I2C I/O
- 5.5V Tolerant I2C and enable input support
- Lockup-free operation
- Powered-off high-impedance I2C bus pins
- Support for clock stretching and multiple controller arbitration across the device
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22
- 4000V Human-body model
- 1500V Charged-device model
The TCA9617B is a BiCMOS dual bidirectional buffer intended for I2C bus and SMBus systems. The device provides bidirectional voltage-level translation (up-translation and down-translation) between low voltages (down to 0.8V) and higher voltages(2.2V to 5.5V) in mixed-mode applications. This device enables I2C and similar bus systems to be extended, without degradation of performance even during level shifting.
The TCA9617B buffers both the serial data (SDA) and the serial clock (SCL) signals on the I2C bus, allowing two buses of 550pF to be connected in an I2C application. This device can also be used to separate two halves of a bus for voltage and capacitance.
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檢視所有 10 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | TCA9617B Level-Translating FM+ I2 C Bus Repeater datasheet (Rev. E) | PDF | HTML | 2024年 10月 2日 |
| Application note | Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) | PDF | HTML | 2024年 7月 3日 | |
| Application note | Why, When, and How to use I2C Buffers | 2018年 5月 23日 | ||
| Technical article | Intro to I2C: what the Internet doesn’t tell you | PDF | HTML | 2016年 11月 24日 | |
| Application note | Choosing the Correct I2C Device for New Designs | PDF | HTML | 2016年 9月 7日 | |
| Selection guide | I2C Infographic Flyer | 2015年 12月 3日 | ||
| Technical article | How to simplify I2C tree when connecting multiple slaves to an I2C master | PDF | HTML | 2015年 10月 15日 | |
| Application note | Understanding the I2C Bus | PDF | HTML | 2015年 6月 30日 | |
| Application note | Maximum Clock Frequency of I2C Bus Using Repeaters | 2015年 5月 15日 | ||
| Application note | I2C Bus Pull-Up Resistor Calculation | PDF | HTML | 2015年 2月 13日 |
設計與開發
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設計工具
I2C-DESIGNER — I2C 設計工具
Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。